Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
1999-09-28
2001-08-07
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S253000, C438S396000, C438S397000, C438S399000, C438S639000, C438S648000, C438S649000, C257S308000, C257S309000, C257S310000
Reexamination Certificate
active
06271099
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the fabrication of integrated circuit devices and, more particularly to a method of forming a capacitor structure with low interfacial reaction and increased capacitance of a dynamic random access memory (DRAM) cell.
BACKGROUND OF THE INVENTION
For ultra large scale integration (ULSI) semiconductor technologies nowadays, the dramatically increased of the integrated circuit density has downsizing the individual devices. Dynamic random access memory (DRAM) circuit is one of the integrated circuit types to experience the demand of increased density, which is used extensively in the electronics industry for information storage. Normally, one can evaluate the development of a semiconductor-manufacturing factory by the minimum conductive line, or the storage capacity of DRAM devices it can produce.
The memory cells of DRAM are comprised of two main components: a field-effect transistor (MOSFET) and a capacitor. A bit line and a word line is connected to source/drain area and gate area of MOSFET cell respectively. The other source/drain area of MOSFET is electrically connected to the capacitor. During operations, the digital signal of bit line is stored to the capacitor via the controlled voltage of word line. A single DRAM storage cell stores a bit of data on the capacitor as electrical charge. As component density in memory chips has increased, the shrinkage of cell capacitor size has resulted in a number of problems. Firstly, &agr;-particle component of normal background radiation will generate hole-electron pairs in the n+silicon substrate plate of a cell capacitor. This phenomena will cause the charge within the affected cell capacitor to rapidly dissipate, resulting in a “soft” error. Secondly, the cell refresh time must be shortened due to the cell capacitance is reduced, thus more refresh interruptions are required.
Owing to all the problems described above, several stacked structures of capacitor are introduced to increase capacitance, such as fin shaped or crown shaped capacitor structure. Alternatively, another scheme involves the use of high dielectric constant materials such as Ta
2
O
5
or BaTiO
3
to further increase the capacitance.
Although the efforts to provide adequate cell capacitance focus on creating complex three-dimensional capacitors and improving the dielectric materials, some problems are still exist in fabricating the DRAM cells. One of the problems is that the conventional lower capacitor node contact comprises semiconductor material such as doped polysilicon layer, which the interfacial reaction is inevitable. Besides, the capacitor node contact filling becomes increasingly difficult as a result of reduced device dimensions. For node contact with high aspect ratio (more than ten), it is not easy to use a Physical Vapor Deposition (PVD) method to fill barrier metal or use a Chemical Vapor Deposition (CVD) method to fill tungsten (W).
Although a considerable work has been done to improve the reliability of DRAM cells, there is still a strong need in the semiconductor industry to further improve the reliability of DRAM cells and to increase the capacitance of the stacked capacitors for DRAM cells. This is especially true when the semiconductor fabrication proceed to next decade.
SUMMARY OF THE INVENTION
The present invention is directed to the fabrication of a DRAM cell. Accordingly, it is a principal object of the present invention to provide a method for fabricating a capacitor with void/seam free deposition of a high aspect ratio node contact.
It is another object of the present invention to provide a method for making a capacitor of metal/insulator/metal (MIM) structure with a high dielectric constant layer.
It is still another object of the present invention to provide a method for making a capacitor with a crown shaped to increase the capacitance.
The above objectives of this invention are achieved by providing a method for fabricating a DRAM cell with a crown shaped MIM structure capacitor. The method begins by forming a field-effect transistor (MOSFET) gate electrode and word line on a substrate. A multilayer gate electrode and word line are composed of a polycide layer and overlaying a cap layer. After the gate electrode and word line are defined, lightly doped source/drain area, sidewall spacers, and heavily doped source/drain area is formed sequentially.
Subsequently, a titanium (Ti)/titanium nitride (TiN) layer serves as a barrier layer, is deposited over the substrate. Next, a tungsten (W) layer and a TiN ARC (anti-reflection coating) layer is formed on the Ti/TiN layer. Conventional photolithographic and reactive ion etching techniques are used to define a metal landing pad.
Next, a first insulating layer is deposited and then a node contact is formed align the metal landing pad by using the tungsten layer of the metal landing pad as an etch stop. After the node contact is formed, a CVD titanium nitride is deposited within the node contact and over the first insulating layer. Then, a reactive ion etching method is used to form titanium nitride spacer in the node contact, the underlayer tungsten serves as an etch stop and is exposed. Forming selective tungsten in the node contact by using exposed tungsten as a seeding layer. The extra tungsten is then etched back by using a reactive ion etching method.
Thereafter, a second insulating layer is formed and planarized over the substrate. Conventional photolithographic and anisotropic plasma etching techniques are used to form an opening in the second insulating layer aligned with the node contact. Then, a metal layer, which serves as the bottom electrode of a stacked capacitor, is deposited by using a CVD method. The metal layer is composed of a titanium nitride and a tungsten layer. Afterwards, a photoresist layer is formed on the metal layer and then a chemical mechanical polishing method is used to remove portions of the photoresist layer and the metal layer by using the second insulating layer as an polishing stop.
A crown shaped bottom electrode is defined after the remaining photoresist and the second insulating layer is removed. Next, a high dielectric constant layer such as Ta
2
O
5
or BaTiO
3
is deposited to act as capacitor dielectric layer. Finally, a titanium nitride layer is formed on the capacitor dielectric layer to complete the crown shaped capacitor.
A crown shaped capacitor with metal/insulator/metal structure, a high reliability of capacitor is achieved. Besides, with high aspect ratio node contact, it is easy for the present invention to fill with selective tungsten without void/seam.
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patent: 6159820 (2000-12-01), Park
patent: 6160013 (2000-08-01), Tu
patent: 6174782 (2001-01-01), Lee
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Keshavan B. V.
Smith Matthew
Worldwide Semiconductor Manufacturing Corp.
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