Electrical computers and digital processing systems: processing – Processing architecture – Superscalar
Reexamination Certificate
2000-06-16
2001-07-03
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Superscalar
C712S218000
Reexamination Certificate
active
06256721
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to the field of processors and, more particularly, to register renaming mechanisms within processors.
2. Description of the Related Art
Superscalar processors attempt to achieve high performance by dispatching and executing multiple instructions per clock cycle, and by operating at the shortest possible clock cycle time consistent with the design. To the extent that a given processor is successful at dispatching and/or executing multiple instructions per clock cycle, high performance may be realized.
One technique often employed by processors to increase the number of instructions which may be executed concurrently is speculative execution (e.g. executing instructions out of order with respect to the order of execution indicated by the program or executing instruction subsequent to predicted branches). Often, instructions which are immediately subsequent to a particular instruction are dependent upon that particular instruction (i.e. the result of the particular instruction is used by the immediately subsequent instructions. Hence, the immediately subsequent instructions may not be executable concurrently with the particular instruction. However, instructions which are further subsequent to the particular instruction in program order may not have any dependency upon the particular instruction and may therefore execute concurrently with the particular instruction. Still further, speculative execution of instruction subsequent to mispredicted branches may increase the number of instructions executed concurrently if the branch is predicted correctly.
Out of order execution gives rise to another type of dependency, often referred to as an “antidependency”. Generally, antidependencies occur if an instruction subsequent to a particular instruction updates a register which is either accessed (read) or updated (written) by the particular instruction. The particular instruction must read or write the register prior to the subsequent instruction writing the register for proper operation of the program. Generally, an instruction may have one or more source operands (which are input values to be operated upon by the instructions) which may be stored in memory or in registers. An instruction may also have one or more destinations (which are locations for storing results of executing the instruction) which may also be stored in memory or in registers.
A technique for removing antidependencies between source and destination registers of instructions, and thereby allowing increased out of order execution, is register renaming. In register renaming, a pool of “rename registers” are implemented by the processor. The pool of rename registers are greater in number than the registers defined by the instruction set architecture employed by the processor (the “architected registers”). The destination register for a particular instruction (i.e. the architected register within with the execution result of the instruction) is “renamed” by reassigning one of the rename registers to the architected register. The value of the architected register prior to execution of the particular instruction remains stored in the rename register previously assigned to the architected register. If a previous instruction reads the architected register, the previously assigned rename register is used. If a previous instruction writes the architected register, the previously assigned register is written. Accordingly, the rename registers may be updated in any order.
Register renaming may also allow speculative update of registers due to instruction execution subsequent to a predicted branch instruction. Previous renames may be maintained until the branch instruction is resolved. If the branch instruction is mispredicted, the previous renames may be used to recover the state of the processor at the mispredicted branch instruction.
While register renaming is useful for removing antidependencies, true dependencies (in which a subsequent instruction uses the result of a particular instruction) cannot be removed using register renaming. If a particular architected register is used repeatedly as a destination and subsequently as a source register in a code sequence, register renaming may not offer much aid in allowing for concurrent execution of instructions. For example the x86 instruction set architecture (also referred to as IA-32 or APX) defines a stack pointer register (ESP) which is often used as both a source and as a destination of a variety of instructions. The stack pointer defines the top of a stack maintained in main memory, within which many operands operated upon by instructions are stored. Due to the relatively small number of registers provided in the x86 instruction set architecture, references to the stack and manipulations of the stack are typically fairly frequent. Accordingly, the stack pointer register is often both a source register and a destination register of instructions.
Additionally, a second architected register in the x86 instruction set is the base pointer (EBP) register. The base pointer register is often used to define a memory location within the stack which is the base address for a variety of operands used by a particular program routine. In order words, the operands used by the routine are stored in memory locations between the memory location identified by the base pointer and the memory locations identified by the stack pointer. Accordingly, moves between the base pointer and stack pointer registers may occur frequently in a program (e.g. at the entrance and exit of a variety of subroutines within the program).
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by an apparatus for accelerating move operations. The apparatus includes a lookahead unit which detects move instructions prior to the execution of the move instructions (e.g. upon selection of the move operations for dispatch within a processor). Upon detecting a move instruction, the lookahead unit signals a register rename unit, which reassigns the rename register associated with the source register to the destination register. The reassignment may comprise reassigning the rename tag identifying the rename register assigned to the source register to the destination register. If the destination register is a register frequently used as a source for subsequent instructions and the source rename register has already been updated upon detection of the move, concurrency may be increased by reassigning the source register's rename register to the destination register. Once the reassignment is performed, the frequently used register has a valid value if the source rename register was valid prior to the reassignment. Accordingly, subsequent dependent instructions may more rapidly be provided with the value from the frequently used register (i.e. prior to execution of the move operation). Performance of a processor employing the apparatus may be increased due to the enhanced concurrency which may be provided.
In one particular embodiment, the lookahead unit attempts to accelerate moves from a base pointer register to a stack pointer register (and vice versa). The stack pointer register may be frequently used a source operand (e.g. an address operand), as many instructions may manipulate operands at the top of the stack. Additionally, the base pointer register may often be held constant within a code sequence and be used as a source for addresses within the stack. Therefore, the rename register associated with the base pointer register may frequently be valid upon detection of a move from base pointer to stack pointer. A lookahead value for the stack pointer register may be thereby be provided prior to execution of the move base pointer to stack pointer instruction by reassigning the base pointer rename register to the stack pointer.
Still further, many manipulations of the stack pointer register than moves may be fixed increments or decrements of the value stored in the stack pointer register. Therefore, an embodiment of the lo
Advanced Micro Devices , Inc.
Coleman Eric
Conley Rose & Tayon PC
Merkel Lawrence J.
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