Delayed deallocation of an arithmetic flags register

Details Delayed deallocation of an arithmetic flags register Delayed deallocation of an arithmetic flags register

1998-12-31

2001-06-26

Donaghue, Larry D. (Department: 2154)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Commitment control or register bypass

C712S023000, C712S234000

Reexamination Certificate

active

06253310

ABSTRACT:

FIELD
The present invention is related to processors, and more particularly to register management in processors.
BACKGROUND INFORMATION
The function of a processor, such as a microprocessor, is to execute programs. Programs comprise a group of instructions. Each instruction is broken down into one or more operations known as micro-operations (referred to herein as “uops”). Processors execute uops by reading operands from one or more source registers and storing results in one or more destination register. A register is a temporary storage area within a processor for holding arithmetic and other results used by the processor. Registers are individually comprised of bits. A bit is a binary digit and represents either a “0” value or a “1” value. Different registers may be used for different functions. For example, general purpose registers are used interchangeably to hold operands for logical and arithmetic operations. Special purpose registers may be used for holding status information via various flag bits, for example.
The term “IA-32” refers to a well known instruction set utilized by an Intel® architecture family of processors, e.g. the Pentium® II microprocessor and the Pentium® Pro microprocessor, manufactured by Intel Corporation. IA-32 defines a special purpose register called an EFLAGS register. The EFLAGS register comprises a 32-bit flag register which holds a group of status flags, control flags, and system flags.
FIG. 1
is a diagram of the EFLAGS register. As shown in
FIG. 1
, the status flags are indicated by an “S,” the control flag is indicated by a “C,” and the system flags are indicated by an “X.” The status flags contained in the EFLAGS register allow the results of one instruction to influence later instructions. The status flags (also called arithmetic flags) include a carry flag at bit “
0
”, a parity flag at bit “
2
”, an auxiliary carry flag at bit “
4
”, a zero flag at bit “
6
”, a sign flag at bit “
7
”, a trap flag at bit “
8
”, and an overflow flag at bit “
11
”. The control flag contained in the EFLAGS register controls string instructions. The control flag of the EFLAGS register is stored at bit “
10
” as shown in FIG.
1
. The system flags of the EFLAGS register control input/output, maskable interrupts, debugging, task switching and enabling of virtual 8086 execution. The system flags are stored in the EFLAGS register at bits “
9
,” “
12
,” “
14
,” “
16
” and “
17
” as shown in FIG.
1
.
Traditionally, a processor had a single instruction set, such as the IA-32 instruction set, for example. Typically, the processor could only accept operating systems and application programs in that instruction set. If a processor architecture and the instruction set are fundamentally altered, the processor is no longer capable of executing an existing software base of operating systems and application programs. As a result, fundamental changes, and therefore, major advances in processor architecture and instruction sets, have not been possible where compatibility with a previous instruction set is a desired design objective.
However, U.S. Pat. No. 5,638,525, ('525 patent) assigned to Intel Corporation, describes a processor architecture capable of accepting multiple operating systems and application programs using different instruction sets. This architecture allows a first program using a first instruction set to execute concurrently with a second program using a different instruction set that is not compatible with the first instruction set. One specific embodiment shown in the '525 patent comprises a microprocessor that can accept both a 32 bit instruction set and a 64 bit instruction set.
The term “compatible” as used herein refers to the ability of an instruction of one instruction set architecture to operate with a different instruction set architecture. For example, the instruction may be from a previous version of the instruction set architecture. In order to provided an improved processor architecture and instruction set while at the same time maintaining compatibility to a previous instruction set, it is desirable to reduce the hardware dedicated to the previous instruction set. The new hardware (such as the execution units and the register set) is used as much as possible to support the previous instruction set.
In order for a processor capable of accepting multiple instruction sets to accept both the IA-32 instruction set or the like and a second instruction set which is not compatible to the IA-32 instruction set or the like, it is desirable that the processor be able to manage the information contained in the IA-32 instruction set EFLAGS register or the like in a manner that is compatible with the second instruction set. If the second instruction set lacks an equivalent to the EFLAGS register or if the second instruction set experiences a significant performance penalty by maintaining the EFLAGS register or a portion of the EFLAGS register in the same manner as provided for by the IA-32 instruction set, then it may not be desirable for the processor to execute an existing software base of operating systems and application programs utilizing the IA-32 bit instruction set or the like.
Accordingly, there is a need for methods and corresponding designs to provide compatibility for the Intel® 32-bit architecture processor instruction set or the like in a multi-instruction set processor architecture.
SUMMARY
According to one aspect of the present invention, a system of the present invention processes instructions of a first instruction set architecture which has an arithmetic flags register.
The system also processes instructions of a second instruction set architecture which is not compatible with the first instruction set architecture. In order to process a first instruction of the first instruction set architecture that implicitly updates the arithmetic flags register, the arithmetic flags register shares a physical destination register with a general register containing a result for the first instruction. An instruction that does not update the arithmetic flags but would deallocate the register containing the arithmetic flags triggers the delayed deallocation mechanism of the present invention.
Still other and further embodiments, aspects and advantages of the invention will become apparent by reference to the drawings and by reading the following detailed description.


REFERENCES:
patent: 5446912 (1995-08-01), Colwell et al.
patent: 5481693 (1996-01-01), Blomgren et al.
patent: 5488730 (1996-01-01), Brown, III et al.
patent: 5638525 (1997-06-01), Hammond et al.
patent: 5802340 (1998-09-01), Mallick et al.
patent: 6047369 (2000-04-01), Colwell et al.
patent: 6061777 (2000-05-01), Cheong et al.
patent: 6098168 (2000-08-01), Eisen et al.
patent: 6170052 (2001-01-01), Morrison
patent: WO 00/07097 (2000-02-01), None

Affiliated with

Also associated with

Rating

Delayed deallocation of an arithmetic flags register does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Delayed deallocation of an arithmetic flags register, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Delayed deallocation of an arithmetic flags register will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2534922