Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1996-03-11
2001-01-09
Chang, Kent (Department: 2778)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S211000, C345S099000
Reexamination Certificate
active
06172663
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention:
The present invention relates to a driver circuit used for driving an active-matrix type liquid crystal display device in which liquid crystal is interposed between a pair of substrates.
2. Description of the Related Art:
In driving a liquid crystal display device, the response speed of the liquid crystal functioning as a display medium is considerably lower than that of a luminescent material used for a cathode-ray tube (CRT). A driver circuit of a particular type is currently used for driving the liquid crystal display device.
The driver circuit for a liquid crystal display device receives image signals sequentially, but does not apply the received image signals to respective pixels sequentially. That is, the driver circuit for a liquid crystal display device holds the image signals which have been sampled so as to correspond to the respective pixels, during one horizontal period. Then, the driver circuit for a liquid crystal display device outputs all the image signals at a time at the beginning or in the middle of the next horizontal period. The driver circuit for a liquid crystal display device continues to output the voltage of the image signals for a time period long enough to charge the respective pixel electrodes with the voltage. The time period during which the voltage continues to be output is called “one output period”. In general, the length of the output period is approximately equal to the length of one horizontal period, in many cases.
A large-scale integrated circuit (LSI) called a “driver” is used for performing the driving method described above. There are two kinds of drivers, i.e., a data driver (also called a column driver or a source driver) for performing the sampling and the image signal output described above, and a scanning driver (also called a row driver or gate driver) for scanning a liquid crystal display device by every horizontal line. In the following description, a data driver will be referred to as a “driver” except in a few special instances.
FIG. 9
is a diagram showing a simplified configuration for a liquid crystal display device
100
and for a driver circuit including data drivers
101
and scanning drivers
102
. S(i) indicates an output from the i-th data driver
101
; G(j) indicates an output from the j-th scanning driver
102
; and P(j, i) indicates a pixel formed at the crossing between the i-th column and the j-th row. The arrows under pixels P(l, i), P(l, i+1), P(j, i), P(j, N), etc. indicate that these pixels are connected with a common electrode.
FIG. 10
is a circuit diagram showing a configuration for the data driver
101
corresponding to one output on the i-th column through which a digitized image signal is supplied. The circuit which has the same configuration as that shown in
FIG. 10
is provided to each of the data electrodes (also called data lines) O
1
to O
N
of the liquid crystal display device
100
.
FIG. 10
shows a case where image signal data is composed of three bits.
When a sampling pulse Tsmp(i) is supplied to an image signal which has been input to the i-th data driver
101
, the signal is stored in an i-th sampling memory Msmp(i). After the sampling is finished for all the circuits in the above way, an output pulse LS is supplied at an appropriate timing, whereby all the data stored in the respective sampling memories Msmp are supplied to holding memories MH at a time. In this case, the data stored in the i-th sampling memory Msmp(i) is supplied to the i-th holding memory MH(i).
The data stored in each holding memory MH is input to a decoder DEC; one of eight analog switches ASW
0
to ASW
7
which corresponds to the value of the data is turned ON; and one of eight gray-scale voltages V
0
to V
7
is output through the analog switch which has been turned ON, thereby driving a corresponding data electrode of the liquid crystal display device
100
. For example, if the value of the data is decimally 2, the level of the output S
2
from the decoder DEC becomes high and the analog switch ASW
2
is turned ON, so that the gray-scale voltage V
2
is output from the circuit.
When one of the eight gray-scale voltages V
0
to V
7
is output from the circuit, the level of the output from the scanning driver
102
corresponding to a scanning electrode (also called a scanning line, a gate line or a row line) of a row to be used for display is high, and all the switching elements on the row turns ON. Then, each of pixel electrodes on the row is charged with the same voltage as the voltage of each corresponding data electrode. In other words, each pixel electrode is charged with the voltage output from the corresponding data driver
101
, via the switching element turned ON.
For example, when the level of the j-th output from the scanning driver
102
becomes high in
FIG. 9
, all the switching elements T(j,
1
) to T(j, N) connected with the scanning electrode Lj are turned ON. Accordingly, the pixels P(j,
1
) to P(j, N) connected with the scanning electrode Lj are charged with the corresponding outputs S(l) to S(N) from the data drivers
101
, respectively.
In driving the liquid crystal display device
100
, it is necessary to invert the polarity of the voltage applied to the liquid crystal at regular intervals for preventing the liquid crystal from being degraded. Such a drive method is called an alternating current (AC) drive method for a liquid crystal display device. This drive method includes inverting the polarity of the output voltage from the driver
101
into positive or negative with respect to a counter electrode. A vertical inversion drive method (or a frame inversion drive method) in which the data voltage polarity is inverted frame by frame is the easiest method for performing the AC drive.
Hereinafter, the frame inversion drive method will be described in detail.
FIGS. 11 and 12
show the waveforms of the respective voltages in the frame inversion drive method in which the gray-scale voltage V
0
is written into all the pixels. Hereinafter, it will be assumed that the voltage V
0
is written into all the pixels, except in some special cases.
In
FIGS. 11 and 12
, S(i) indicates an output from the i-th data driver
101
; G(j) indicates an output from the j-th scanning driver
102
, as the same manner in FIG.
9
. In
FIGS. 11 and 12
, Hsyn indicates a horizontal synchronizing signal; LS indicates an output pulse as described referring to
FIG. 10
; and GCK indicates a clock signal for operating the scanning driver. The output pulses LS are sequentially output in synchronization with the leading edges of the respective clock signals GCK. In the following description, P(j, i), etc. indicates the potential level of a pixel.
As shown in
FIG. 11
, when the output pulse LSj is supplied, a voltage corresponding to the image data which has been supplied during the horizontal period Hj is output. During the horizontal period Hj+1, the level of the output G(j) from the j-th scanning driver is high, and the pixel P(j, i) is charged via the switching element T(j, i) so as to reach the level of the output voltage +VO of the output S(i) of the i-th data driver, as indicated by the arrow A in FIG.
11
. That is, the potential of the P(j, i) is varied from the potential level −V
0
in the previous frame to the potential level +V
0
during the period Hj+1.
When the level of the output G(j) from the j-th scanning driver
102
becomes low, the switching element T(j, i) is turned OFF. As a result, the charges are held in the pixel P(j, i) and the potential level +V
0
is maintained until the beginning of the write period in the next frame, i.e., the beginning of the horizontal period Hj+1 in FIG.
12
. As indicated by the arrow A′ in
FIG. 12
, the potential level of the pixel P(j, i) is inversely varied from +V
0
to −V
0
during the horizontal period Hj+1.
In case of the frame inversion drive method, the level of the output voltage S(i) from the i-th data driver
101
is positive +V
0
all throu
Etou Sunao
Okada Hisao
Yamamoto Yuji
Chang Kent
Nixon & Vanderhye P.C.
Sharp Kabushiki Kaisha
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