Method for removal of etch residue immediately after etching...

Semiconductor device manufacturing: process – Chemical etching

Reexamination Certificate

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Details

C438S697000, C438S706000, C438S745000

Reexamination Certificate

active

06277747

ABSTRACT:

BACKGROUND OF THE INVENTION
During manufacture of a semiconductor device, interconnect layers are often created using aluminum or other conductive elements and compounds. Following formation of an interconnect, a spin-on-glass (SOG) plasma etch back step is performed to planarize the exposed semiconductor surface, including the exposed aluminum interconnect and an anti-reflective coating (ARC). A titanium compound forms in globs, or bumps on the semiconductor wafer during SOG etch back when the ARC film is exposed to the plasma. The bumps remain on the wafer, and are easily seen in high concentrations at 40×, all over the wafer. The bumps can be 1000 Angstroms or greater in both height and width. As a result, the semiconductor product must be scrapped.
Past attempts at cleaning or otherwise removing titanium containing bumps on semiconductor leads have resulted in peeling of the fully manufactured semiconductor. Some attempts have resulted in faulty semiconductors, i.e. having poison vias.
It is therefore an object of the present invention to safely manufacture semiconductors having interconnect leads and anti-reflective coating. It is another object of the invention to perform an etching process on such a semiconductor without permanent formation of titanium-containing clusters or bumps, especially on the interconnect leads. It is yet another object of the present invention to manufacture such a semiconductor without detrimental effects to the final product such as peeling and poison vias.
SUMMARY OF THE INVENTION
The present invention is directed to a semiconductor manufacturing method, which includes the steps of: forming an interconnect layer, which may comprise aluminum, on a semiconductor substrate; forming an anti-reflective coating; forming a spin on glass layer; selectively etching portions of the spin on glass layer, whereby predetermined portions of the interconnect layer are exposed; and applying an EKC solution to predetermined portions of the interconnect layer that are exposed.
The semiconductor manufacturing may also include the steps of forming a first tetra-ethyl-ortho-silicate layer, before the step of forming a spin on glass layer; and forming a second tetra-ethyl-ortho-silicate layer, following the step of applying an EKC solution. The EKC solution in the preferred embodiment has a three day bath life and is applied for at least about a 10 minute process time. Furthermore, the semiconductor manufacturing method may include the step of forming a second interconnect layer.
The semiconductor manufacturing method may further include forming an anti-reflective cover layer which comprises titanium in elemental form, or as a compound with other elements, prior to the step of selectively etching portions of the spin on glass layer.
Another embodiment of the present invention is directed to a semiconductor manufacturing method, which includes the steps of: forming an interconnect layer, and an anti-reflective layer, on a semiconductor substrate; forming a spin on glass layer; selectively etching portions of the spin on glass layer, so that predetermined portions of the interconnect layer and the anti-reflective layer are exposed; and subjecting the semiconductor substrate and at least a portion of the interconnect layer to a treatment so that a residual product of the selectively etching step is removed. The residual product of the selectively etching step may include clusters of TiON. In a preferred embodiment, these clusters chemically react with a solution comprising EKC.


REFERENCES:
patent: 5733712 (1998-03-01), Tanaka et al.
patent: 5798568 (1998-08-01), Abercrombie et al.
patent: 5854503 (1998-12-01), Hsueh et al.
patent: 5880018 (1999-03-01), Boeck et al.
patent: 5902780 (1999-05-01), Lee
patent: 5937324 (1999-08-01), Abercrombie et al.

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