Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal
Reexamination Certificate
1999-06-22
2001-03-20
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making device or circuit emissive of nonelectrical signal
C438S022000
Reexamination Certificate
active
06204078
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a photonic semiconductor device such as a laser diode, and more particularly, to a method of fabricating a photonic semiconductor device equipped with a diffraction grating and an optical waveguide on a semiconductor substrate, at least part of the optical waveguide being located on the diffraction grating.
2. Description of the Prior Art
In general, to control accurately the width of an optical waveguide is one of the most important matters for ensuring the desired performance and fabrication yield of a photonic semiconductor device. As one of the methods realizing such accurate control, the selective Metal-Organic Vapor Phase Epitaxy (MOVPE) has been known well and practically used.
In the MOVPE process, first, a dielectric mask layer, which is, for example, made of silicon dioxide (SiO
2
), is formed on a flat surface of a semiconductor substrate. The mask layer has a strip-shaped window that exposes a desired part of the flat surface of the substrate. Next, specific semiconductor layers are selectively and successively grown through the strip-shaped window on the exposed part of the surface using the selective MOVPE process, thereby forming a strip-shaped optical waveguide with a multilayer structure on the flat surface of the substrate. The optical waveguide (i.e., the stacked semiconductor layers) has a strip-like plan shape corresponding to that of the window of the mask layer and extends along the surface of the substrate. Thereafter, the dielectric mask layer is removed.
As seen from the above explanation, when the selective MOVPE process is used, the accuracy of the width of the optical waveguide is determined by the accuracy of the strip-shaped window of the dielectric mask layer, in other words, the accuracy of a patterning process for the mask layer.
A possible accuracy of the patterning process for the dielectric mask layer is approximately ±0.1 &mgr;m, which is approximately equal to that of patterning processes used in popular semiconductor device fabrication. Therefore, when the selective MOVPE process is used, there is an advantage that the controllability of the width of the waveguide can be remarkably improved, compared with a case where stacked semiconductor layers are formed on a flat surface of a semiconductor substrate and then, the stacked semiconductor layers are patterned to form an optical waveguide. Because of the advantage of excellent controllability, the selective MOVPE process has been popularly used in fabrication of miniaturized photonic semiconductor devices such as laser diodes.
An example of the prior-art methods of fabricating a photonic semiconductor device using the selective MOVPE process is schematically shown in
FIGS. 1A and 1B
, which fabricates a Distributed-FeedbBack (DFB) type semiconductor laser device equipped with a laser element and an optical modulator element formed on a semiconductor substrate. This prior-art method is disclosed in the Japanese Non-Examined Patent Publication No. 7-176822 published in July 1995.
In the prior-art method shown in
FIGS. 1A and 1B
, first, a patterned resist film (not shown) is formed on a flat surface of an n-type indium phosphide (InP) substrate
101
. The patterned resist film is usually obtained by electron-beam (EB) exposure and development. Next, using the patterned resist film as a mask, the flat surface of the InP substrate
101
is selectively etched, forming parallel grooves on a desired part of the flat surface of the substrate
101
, as shown in FIG.
1
A. The grooves, which are arranged at regular intervals, constitute a diffraction grating
102
.
At this stage, the flat surface of the substrate
101
is divided into two areas, a grooved area
105
and a non-grooved, flat area
106
, due to the formation of the diffraction grating
102
. The grooves or grating
102
are located in only the groove area
105
.
Subsequently, a SiO
2
layer (not shown) is deposited on the whole surface of the substrate
101
and then, it is patterned by etching using a patterned photoresist film as a mask. The patterned photoresist film is usually obtained by photolithography. The patterned SiO
2
layer thus foamed on the flat surface of the substrate
101
serves as a growth-inhibiting mask layer
107
shown in FIG.
1
B. The mask layer
107
has a pair of strip-like masking parts
107
a
and
107
b
and a strip-shaped window
108
intervening between the masking parts
107
a
and
107
b.
The masking parts
107
a
and
107
b
and the window
108
extend over not only the flat area
106
but also the grooved area
105
. The width of the masking parts
107
a
and
107
b
in the grooved area
105
is larger than that in the flat area
106
.
Thereafter, using the growth-inhibiting mask layer
107
, specific semiconductor layers (not shown) are selectively and successively grown through the window
108
on the flat surface of the substrate
101
by a selective MOVPE process, forming a strip-shaped optical waveguide (not shown) with a multilayer structure on the exposed surface of the substrate
101
. The optical waveguide (i.e., the stacked semiconductor layers) has a strip-shaped plan shape corresponding to that of the window
108
of the mask layer
107
and extends along the surface of the substrate
101
. Thereafter, the mask layer
107
is removed.
Finally, specified semiconductor and dielectric layers (not shown) are successively formed to cover the strip-shaped optical waveguide and then, specified electrodes (not shown) are formed, completing a DFB type semiconductor laser device with an incorporated optical modulator element.
The Japanese Non-Examined Patent Publication Nos. 6-314657 published in November 1994 and 9-186391 published in July 1997 disclose similar prior-art fabrication methods to that shown in
FIGS. 1A and 1B
.
With the prior-art method of fabricating a photonic semiconductor device shown in
FIGS. 1A and 1B
, after the diffraction grating
102
is formed on the flat surface of the substrate
101
, the SiO
2
layer is deposited thereon and patterned to form the dielectric mask layer
107
. Thus, there is a problem of performance degradation of the fabricated photonic device and low fabrication yield thereof, the reason of which is as follows.
First, since the SiO
2
layer for the masking layer
107
is formed directly on the diffraction grating
102
in the grooved area
105
of the substrate
101
, the level of flatness of the SiO
2
layer in the grooved area
105
is lower than that in the flat area
106
due to existence of the grating
102
. Accordingly, when the resist film is formed on the SiO
2
layer for the purpose of patterning the same, the resist film is liable to have excessive or intolerable fluctuation in thickness in the grooved area
105
due to the low-level flatness of the SiO
2
layer.
Also, since the low-level flatness of the SiO
2
layer for the mask layer
107
lowers its adherence to the overlying resist film, a so-called side-etch rate will increase in the etching or patterning process of the SiO
2
layer.
As a result, the etching or patterning accuracy of the SiO
2
layer in the grooved area
105
is lower than that in the flat area
106
, which increases the deviation in the width of the window
108
of the mask layer
107
in the grooved area
105
. This width deviation of the window
108
will increase the deviation in the width of the optical waveguide in the grooved area
105
, resulting in the above-described problem that the performance of the fabricated photonic device (e.g., degradation of the light-emitting characteristics of the laser element) is degraded and its fabrication yield is lowered.
Second, the etching or patterning accuracy of the SiO
2
layer for the mask layer
107
is not lowered in the flat area
106
and therefore, considerable difference will occur in the etching or patterning accuracy of the SiO
2
layer between the grooved and flat areas
105
and
106
. Accordingly, the width of the strip-shaped window
1
McGinn & Gibb PLLC
NEC Corporation
Nelms David
Nhu David
LandOfFree
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