Pulse or digital communications – Receivers – Interference or noise reduction
Reexamination Certificate
1998-01-09
2001-06-05
Chin, Stephen (Department: 2734)
Pulse or digital communications
Receivers
Interference or noise reduction
C375S350000, C455S296000
Reexamination Certificate
active
06243430
ABSTRACT:
BACKGROUND OF THE INVENTION
I. Field of the Invention
The present invention relates to communications. More particularly, the present invention relates to a novel and improved noise cancellation circuit and quadrature downconverter.
II. Description of the Related Art
In many modern communication systems, digital transmission is utilized because of improved efficiency and the ability to detect and correct transmission errors. Exemplary digital transmission formats include binary phase shift keying (BPSK), quaternary phase shift keying (QPSK), offset quaternary phase shift keying (OQPSK), m-ary phase shift keying (m-PSK), and quadrature amplitude modulation (QAM). Exemplary communication systems which utilize digital transmission include code division multiple access (CDMA) communication systems and high definition television (HDTV) systems. The use of CDMA techniques in a multiple access communication system is disclosed in U.S. Pat. No. 4,901,307, entitled “SPREAD SPECTRUM MULTIPLE ACCESS COMMUNICATION SYSTEM USING SATELLITE OR TERRESTRIAL REPEATERS”, and U.S. Pat. No. 5,103,459, entitled “SYSTEM AND METHOD FOR GENERATING WAVEFORMS IN A CDMA CELLULAR TELEPHONE SYSTEM”, both assigned to the assignee of the present invention and incorporated by reference herein. An exemplary HDTV system is disclosed in U.S. Pat. No. 5,452,104, U.S. Pat. No. 5,107,345, and U.S. Pat. No. 5,021,891, all three entitled “ADAPTIVE BLOCK SIZE IMAGE COMPRESSION METHOD AND SYSTEM”, and U.S. Pat. No. 5,576,767, entitled “INTERFRAME VIDEO ENCODING AND DECODING SYSTEM”, all four patents are assigned to the assignee of the present invention and incorporated by reference herein.
In the CDMA system, a base station communicates with one or more remote stations. The base station is typically located at a fixed location. Thus, power consumption is less important consideration in the design of the base station. The remote stations are typically consumer units which are produced in high quantity. Thus, cost and reliability are important design considerations because of the number of units produced. Furthermore, in some applications such as a CDMA mobile communication system, power consumption is critical because of the portable nature of the remote station. Tradeoffs between performance, cost, and power consumption are usually made in the design of the remote stations.
In digital transmission, the digitized data is used to modulated a carrier sinusoid using one of the formats listed above. The modulated waveform is further processed (e.g. filtered, amplified, and upconverted) and transmitted to the remote station. At the remote station, the transmitted RF signal is received and demodulated by a receiver.
A block diagram of an exemplary super-heterodyne receiver of the prior art which is used for quadrature demodulation of QSPK, OQPSK, and QAM signals is illustrated in FIG.
1
. Receiver
100
can be used at the base station or the remote station. Within receiver
100
, the transmitted RF signal is received by antenna
112
, routed through duplexer
114
, and provided to front end
102
. Within front end
102
, amplifier (AMP)
116
amplifies the signal and provides the signal to bandpass filter
118
which filters the signal to remove undesirable images and spurious signals. The filtered RF signal is provided to mixer
120
which downconverts the signal to as intermediate frequency (IF) with the sinusoid from local oscillator (LO
1
)
122
. The IF signal from mixer
120
is filtered by bandpass filter
124
and amplified by automatic gain control (AGC) amplifier
126
to produce the required signal amplitude at the input of analog-to-digital-converters (ADCs)
140
. The gain controlled signal is provided to demodulator
104
. Within demodulator
104
, two mixers
128
a
and
128
b
downconvert the signal into the baseband I and Q signals with the sinusoid provided by local oscillator (LO
2
)
134
and phase shifter
136
, respectively. The baseband I and Q signals are provided to lowpass filters
130
a
and
130
b
, respectively, which provide match filtering and/or anti-alias filtering of the baseband signals. The filtered signals are provided to ADCs
140
a
and
140
b
which sample the signals to produce the digitized baseband samples. The samples are provided to baseband processor
150
for further processing (e.g. error detection, error correction, and decompression) to produce reconstructed estimates of the transmitted data.
The first frequency downconversion with mixer
120
allows receiver
100
to downconvert signals at various RF frequencies to a fixed IF frequency where more signal processing can be performed. The fixed IF frequency allows bandpass filter
124
to be implemented as a fixed bandpass filter, such as a surface acoustic wave (SAW) filter, to remove undesirable images and spurious signals from the IF signal. Removal of images and spurious signals is important since these signals can fold into the signal band (e.g. the band where the input signal is present) at the second frequency downconversion stage. Furthermore, the images and spurious signals can significantly increase the amplitude of the signal into various active components, such as the amplifiers and mixers, which can cause higher level of intermodulation products as the result of non-linearity in the active components. Spurious signals and intermodulation products can cause degradation in the performance of the communication system.
The quadrature demodulator of the prior art has several major drawbacks. First, the required filtering by bandpass filter
124
and/or lowpass filters
130
can be complex. These filters may require a flat passband, high attenuation in the stopband, and sharp roll-off in the transition band. These filters are often implemented with analog circuits. Component tolerance of analog circuits is difficult to maintain and can cause distortion in the frequency response of these filters. The performance of receiver
100
can be degraded as the result of the distortion. Second, quadrature balance is difficult to maintain over many production units because of component tolerance in phase splitter
136
, mixers
128
, lowpass filters
130
, and ADCs
140
. Any mismatch in the two signal paths results in quadrature imbalance and degradation in the performance of receiver
100
. Path mismatch results in cross-talk of the I signal onto the Q signal, and vice versa. The cross-talk signal behaves as additive noise in the desired signal and results in poor detection of the desired signal. And third, ADCs
140
can cause degradation in the performance of receiver
100
for various reasons described below.
In most demodulators, one or more ADCs are required to convert an analog waveform in continuous time into discrete samples at evenly spaced time intervals. Some important performance parameters of an ADC include dynamic range, linearity, and DC offset. Each of these parameters can affect the performance of the communication system. Dynamic range can affect the bit-error-rate (BER) performance of the receiver because the noise from the ADC degrades the ability of the ADC to properly detect the input signal. Linearity relates to the difference between an actual transfer curve (e.g., digital output versus analog input) and the ideal transfer curve. Good linearity is more difficult to obtain as the number of bits in the ADC increases. Poor linearity can degrade the error detection/correction process. Finally, DC offset can degrade the performance of the phase locked loop in the receiver and the error correcting decoder, such as the Viterbi decoder.
In the prior art, flash ADCs or successive approximation ADCs are used to sample the baseband signals. Within the flash ADC, the input signal is provided to L−1 comparators, where L=2
m
and m is the number of bits in the ADC. Also provided to each comparator is a comparison voltage. The L−1 comparison voltages are generated by a resistive ladder comprising L resistors. Flash ADCs are bulky and consume high power because L−1 comparators and L resistors are
Brown Charles D.
Chin Stephen
Deppe Betsy L.
Edwards Christopher O.
Qualcomm Incorporated
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