Low mismatch complementary clock generator

Details Low mismatch complementary clock generator Low mismatch complementary clock generator

1999-07-14

2001-01-30

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S170000, C327S277000, C327S291000

Reexamination Certificate

active

06181185

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to clock buffer circuits used in integrated circuits, and, more particularly, to a clock buffer circuit for generating a complementary clock signal from a single-ended clock signal.
BACKGROUND OF THE INVENTION
The performance of very large scale integration (VLSI) systems has been improved by designing hardware that can handle greater clock frequencies. Since pipelined data processing systems generally use clocks which are generally a pair of differential symmetric clocks generated by a centralized clocking circuit, the skew and the rise/fall times of the clocking signals need to be well controlled. If the skew is large, slow or mismatched clock signals can result. This causes errors in the pipeline. Such errors are herein referred to as clock signal races and may be characterized by pipeline situations in which data in one stage “sneaks” through to a subsequent stage before the proper clocking signal is received. These “sneaks” cause lost data.
Top prevent these errors, conventional techniques may use differential clock signals in which one clock signal has a rising edge which occurs after a falling edge of the other clock signal and a falling edge which occurs before a rising edge of the other clock signal. Such signals prevent clock signal races in a pipelined circuit by deactivating a subsequent stage before data is allowed to propagate through the current stage. While such a clocking system prevents data from “sneaking” through to the next stage, it does so at significant performance cost due to the “dead” time between clock edges.
Global overlapping clocks may provide timing advantages with respect to non-overlapping clocks in that there is no dead time between a falling edge of one clock signal and the rising edge of the other clock signal. As a result, early clock edges may be received which allow improved system performance of the pipelined circuits. Global overlapping clocks may be easier to distribute to the circuitry without closely controlling the clock skew caused by time/phase shifts. However, as just noted, if the clock skew is large, race conditions may be created which may cause information to be lost when only global overlapping clocks are used for clocking the pipelined circuits. Furthermore, global overlapping clocks require the distribution of two clock signals. The distribution of two signals instead of one requires extra resources. Finally, the clock skew caused by time/phase shifts of the global overlapping clocks increases the amount of dead time necessary. As the dead time increases, it reduces the amount of time available for other circuitry to do its job. This cuts performance.
SUMMARY OF THE INVENTION
A preferred embodiment of the invention provides two complementary clocks that are well matched from a single input clock. These well-matched clocks help prevent clock race conditions. A single input clock requires fewer resources to distribute globally.
An embodiment of a clock buffer according to the present invention includes an alternating series of edge-rate-controlled inverters and level restoring inverters. The output of this series of inverters is compared to the input clock by a race timer. If the output of the series of inverters switches in the opposite direction before the input clock, the edge rates of the series of inverters are slowed down. If the output of the series of inverters switches in the opposite direction after the input clock, the edge rates of the series of inverters are speeded up. Accordingly, the output of the series of inverters eventually approaches the timing of input clock but complemented. These signals are then optionally buffered and inverted one more time to produce a pair of complementary clocks with well matched timing and appropriately strong drive capability.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.


REFERENCES:
patent: 4899071 (1990-02-01), Morales
patent: 5231319 (1993-07-01), Crafts et al.

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