Undersampling digital testability circuit

Details Undersampling digital testability circuit Undersampling digital testability circuit

1993-07-22

1998-10-20

Decady, Albert

Excavating

371 201, G06F 1100

Patent

active

058257861

ABSTRACT:
An undersampling digital testability circuit 20 includes a bus 15, a data capture array 22 and a divider circuit 18. Divider circuit 18 provides an enablement signal to data capture array 22 that undersamples data travelling along the bus 15 at high data rates thereby effectively testing the integrity of high data rate transfers without the disadvantages of prior art test methodologies.

REFERENCES:
patent: 5196834 (1993-03-01), Edelson et al.
patent: 5277863 (1994-01-01), Bilbrey et al.
patent: 5287100 (1994-02-01), Guttag et al.
patent: 5293468 (1994-03-01), Nye et al.
patent: 5309551 (1994-05-01), Guttag et al.
Chasters A 1-Micron CMOS 128 MHZ video serialiser Palette, and Digital to Analogue (DAC) chip IEEE 1989 p. 117.

Affiliated with

Also associated with

Rating

Undersampling digital testability circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Undersampling digital testability circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Undersampling digital testability circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-253292