Metal working – Method of mechanical manufacture – Electrical device making
Reexamination Certificate
1999-11-16
2001-03-27
Gerrity, Stephen F. (Department: 3729)
Metal working
Method of mechanical manufacture
Electrical device making
C029S825000, C029S847000, C427S097100
Reexamination Certificate
active
06205658
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for formation of metal wiring. More particularly, the present invention relates to a method for formation of metal wiring, which comprises forming, in each groove or via hole formed in the inter-layer insulating film formed on a substrate, a barrier film and a metal film in this order and then flattening the surface of the resulting substrate to fill the groove or via hole with the metal film.
2. Description of the Related Art
As the method for formation of damascene interconnection, etc., there has been employed a method which comprises forming an insulating film on a substrate, forming grooves or the like in the insulating film, filling the grooves with a wiring material to form a wiring, and polishing and flattening the surface of the resulting substrate.
This conventional method is described sequentially on a case of forming a copper wiring. FIGS.
5
(
a
) to
5
(
d
) are sectional views showing the steps employed in the conventional method for formation of damascene interconnection.
First, an inter-layer film
2
made of SiO
2
is formed on a substrate
1
in a thickness of, for example, 1 &mgr;m [FIG.
5
(
a
)]. Successively, grooves
3
having a depth of, for example, 50 nm are formed, by photolithography, at a position of the inter-layer film where a wiring is to be formed [FIG.
5
(
b
)]; then, there is formed, by PVD, a barrier film
4
consisting of a Ta film having a thickness of about 30 nm and a TaN film having a thickness of about 100 nm; further, a copper film
5
is formed in a thickness of about 1 &mgr;m by plating [FIG.
5
(
c
)].
Next, the portions of the copper film
5
and the barrier film
4
present on the inter-layer film
2
, other than the film
5
and the film
4
present in the grooves are removed by polishing, for surface flattening.
The above polishing may be conducted by mechanical polishing which comprises contacting a to-be-polished surface with a rotating turn table while dropping a solution of abrasive grains onto the surface. With this mechanical polishing, as shown in FIGS.
5
(
c
) and
5
(
d
), the initial non-uniformity (in thickness) of the to-be-polished surface remains per se in the surface after polishing; therefore, when a wiring is formed by plating as in the case of formation of copper wiring, the initial non-uniformity in surface smoothness is high and it is impossible to obtain the flatness required for semiconductor device. Hence, there was proposed chemical mechanical polishing (CMP) which comprises polishing a to-be-polished material while simultaneously applying chemical etching to the material. This CMP is mainly used currently.
In CMP, there is used an abrasive obtained by adding, to a slurry containing abrasive grains (e.g. alumina grains), an acid (e.g. hydrochloric acid) and an oxidizing agent (e.g. hydrogen peroxide); however, it is known that when the polishing rate of wiring material (e.g. copper film) is higher than the polishing rate of barrier film (that is, the factor of chemical etching is large) and when polishing is made in one stage so as to reach the barrier film, the copper film recedes in the grooves and large recesses
61
are generated, as shown in FIG.
6
(
a
). This phenomenon is striking particularly when the polishing rate ratio of copper film and barrier film is high.
In CMP, there is other problem. That is, when the polishing rate of conductive film is larger than the polishing rate of insulating film, there is a difference in the polishing pressure applied to the surface of insulating film, between the pattern-concentrated region where the wiring pattern is concentrated and the non-pattern region where the wiring pattern is not formed substantially; as a result, the insulating film is polished in a larger amount in the pattern-concentrated region than in the non-pattern region and, as shown in FIG.
6
(
b
), the pattern-concentrated region is dented as a whole and a dent
62
is formed (this phenomenon is called erosion of insulating film).
In CMP, there is further known the following problem. That is, since the oxide film of the pattern-concentrated region is polished mechanically by the abrasive grains (e.g. alumina grains) contained in the abrasive used, for a ling time, the surface of the oxide film of the pattern-concentrated region comes to have a large number of dishings of several tens of micrometers in diameter, or a large number of mars (called microscratches) of about several nanometers to several hundreds of nanometers in depth, depending upon the length of the polishing time.
In order to eliminate the above problems of erosion and microscratches, it is proposed in, for example, JP-A-10-214834 to carry out:
a first polishing stage of contacting chemical mechanical polishing with a first abrasive having a such a polishing rate ratio that the polishing rate of lower conductive film is smaller than the polishing rate of upper conductive film, in order to remove the upper conductive film other than the groove portion but leave the lower conductive film unremoved, and
a second polishing stage of conducting chemical mechanical polishing with a second abrasive having such a polishing rate ratio that the polishing rate of lower conductive film is about equal to the polishing rate of insulating film, in order to completely remove the lower conductive film other than the dent portion but leave the insulating film unremoved, to obtain a flat film with no erosion.
However, in the above technique, there is selected in the first polishing stage, an abrasive having such a polishing rate ratio that the polishing rate of lower conductive film is ½ or smaller (⅕ in Examples) of the polishing rate of upper conductive film; with such an abrasive, recesses of no small numbers are generated in the upper conductive film. When in the second polishing stage, CMP is conducted with an abrasive showing about the same polishing rate for oxide film and upper conductive film, the above recesses are per se reflected in the final semiconductor device. Hence, in order to eliminate these recesses, it is necessary to use such an abrasive that the polishing rate of oxide film is slightly larger than the polishing rate of upper conductive film. However, when the polishing rate of oxide film is too large, the upper conductive film comes to project depending upon the depth of the recesses. The presence of such recesses or projections tends to cause accumulation of contaminants at their corners, which gives an adverse effect on the properties of the semiconductor device obtained.
In view of the above situation, it is necessary to select the abrasives used in the first polishing stage and the second polishing stage, so that they have a particular relation, and the selection must be made every time when the materials of upper conductive film, lower conductive film and insulating film as well as the designs thereof are changed. Selection of the optimum combination of abrasives is very difficult and complicated.
Further, since the depth of recess varies in each wiring, the height of wiring varies not only in a single substrate but also between substrates, and this invites serious consequences.
SUMMARY OF THE INVENTION
The object of the present invention is to provide an excellent method for formation of metal wiring, which can eliminate the above-mentioned recess or erosion problem and wherein the selection of the abrasive suitable for the materials to be polished is easy and the formed wirings have the same height in a single substrate and also between a plurality of substrates of the same kind.
According to the present invention, there is provided a method for formation of metal wiring, which comprises at least:
a step of forming an insulating film on the principal surface of a substrate,
a step of forming, in the insulating film, grooves or via holes,
a step of forming, on the whole principal surface of the resulting substrate, a barrier film and a metal film in this order, and
a step of
Gerrity Stephen F.
NEC Corporation
Sands Rhonda E
Sughrue Mion Zinn Macpeak & Seas, PLLC
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