Integrated sense and switch circuitry for transformer core...

Details Integrated sense and switch circuitry for transformer core... Integrated sense and switch circuitry for transformer core...

2000-03-07

2001-08-28

Sterrett, Jeffrey (Department: 2838)

Electric power conversion systems

Current conversion

Including automatic or integral protection means

C363S020000, C363S131000

Reexamination Certificate

active

06282107

ABSTRACT:

BACKGROUND OF THE INVENTION
This patent relates to integrated transformer core resetting.
FIG. 1
shows a single ended forward power converter
10
comprising an active reset circuit
20
of the kind described in Vinciarelli, 5,805,434, “Control of Stored Magnetic Energy in Power Converter Transformers” (the “'434 Patent”, incorporated in its entirety by reference). In the Figure, the reset circuit
20
comprises a MOSFET reset switch
30
and its associated intrinsic body diode
32
; a clamp diode
34
; a reset capacitor
36
; a sense diode
38
and a source of sense current
40
of value Isense. An impedance block
42
represents circuit elements connected to the current source
40
for sensing a voltage Vs. The relative timing of the reset switch
30
and a main switch
14
are controlled, as explained in the '434 Patent, to enable the core of the transformer
12
to be reset during each operating cycle. Active core reset circuits are also described in Vinciarelli. U.S. Pat. Re. 36,098 (“the Reissue Patent”, incorporated in its entirety by reference).
Idealized steady-state operating waveforms for the reset circuit
20
are shown in
FIGS. 2A through 2E
. During the time that the main switch
14
is turned on (e.g., between time t=0 and time t=t1) energy is transferred forward from the input voltage source, via the transformer
12
, toward the load
18
and magnetizing energy builds up in the core of the transformer
12
. Between time t1 when the main switch is opened, and time t3, the magnetizing energy stored in the transformer
12
is recycled in the closed resonant circuit formed by the transformer magnetizing inductance and the reset capacitor
36
, resulting in a “mirroring” of the flux in the transformer. This is reflected as a reversal in the flow of magnetizing current (FIG.
2
C), I
R
, which flows in the reset circuit
20
. Although the voltage across the reset capacitor
36
, Vc, will vary owing to the variation in the flow of magnetizing current, and may also vary substantially with operating conditions (as explained in the '434 patent), it can, for purposes of explanation, be considered essentially constant and unipolar (FIG.
2
D). As explained in the '434 patent, clamp diode
34
is used to prevent reversal of voltage across the storage capacitor, and associated undesirable side effects, under certain operating conditions in certain kinds of converters.
Because the relative timing of the opening and closing of the main switch
14
and the reset switch
30
is important (e.g., moments t4 and t5 in FIG.
2
), it is beneficial to generate a signal which indicates that the main switch
14
has opened for use in determining when the reset switch
30
may be closed. As explained in the '434 patent, it is also useful to sense when the magnetizing current changes polarity as this information can be used to inhibit turn-on of the main switch as a means of preventing transformer
12
saturation under transient conditions.
Sense diode
38
and current source
40
are used to sense when the main switch
14
has opened and when the magnetizing current reverses polarity. With reference to
FIG. 2E
, between time t=0 and t=t1 the main switch is closed, the sense diode
38
is reverse biased and the voltage Vs is at a high level (owing to the current Isense from current source
40
flowing in sensing circuit impedance
42
). Opening of the main switch
14
at time t=t1 results in a flow of magnetizing current in the intrinsic diode
32
. Assuming an idealized case in which both the intrinsic diode
32
and the sense diode
38
have the same forward voltage drop, this will cause the voltage Vs to drop to essentially zero volts. At time t3, when the magnetizing current reaches zero, the voltage at the cathode of the sense diode also goes to zero and the voltage Vs takes a step equal to the forward voltage drop of the sense diode
38
. Thereafter, throughout the remainder of the time that the reset MOSFET is carrying current, the voltage at the anode will rise linearly (
FIG. 2E
) owing to the increasing current flowing in the essentially constant on-resistance of the reset MOSFET. The cycle repeats beginning at time t5. As explained in the '434 patent, the steps in the Vs waveform at times t1 and t3 may be used to sense the opening of the main switch and the time at which the polarity of the magnetizing current reverses, respectively.
SUMMARY OF THE INVENTION
In general, in one aspect the invention features an integrated circuit having a MOSFET comprising a drain terminal, a source terminal and a gate control terminal, the MOSFET having an equivalent circuit that includes an intrinsic diode; and a diode comprising an anode terminal and a cathode terminal.
Implementations of the invention may include one or more of the following features. The integrated circuit may include a second diode having a second anode terminal and a second cathode terminal. The cathode terminal and the second cathode terminal may be connected to the drain terminal. The MOSFET may include a sensefet having two source terminals. The integrated circuit may include terminations for making connections to the drain terminal, the source terminal, the gate control terminal and the anode terminal. The integrated circuit may include terminations for making connections to both of the source terminals. The integrated circuit may include a termination for making a connection to the second anode terminal. The MOSFET may have an equivalent circuit including an intrinsic diode, the cathode of the intrinsic diode may be connected to the drain terminal, and the anode of the intrinsic diode may be connected to the source terminal.
The diode may comprise another MOFET integrated onto the die, the other MOSFET may have a channel connected between a drain terminal and a source terminal and a gate control terminal for controlling the conductivity of the channel. The other MOSFET may have an equivalent circuit having an intrinsic diode, the cathode of the intrinsic diode being connected to the drain terminal of the other MOSFET and the anode of the intrinsic diode being connected to the source terminal of the other MOSFET. The channel of the other MOSFET may be rendered non-conductive and the cathode terminal includes the drain terminal of the other MOSFET and the anode terminal includes the second source terminal of the other MOSFET. The other MOSFET may be rendered non-conductive by a connection between the gate control terminal and the source terminal of the other MOSFET.
The second diode may include an additional MOSFET integrated onto the die, the additional MOSFET including a channel connected between a drain terminal and a source terminal and a gate control terminal for controlling the conductivity of the channel. The additional MOSFET is of the kind that has an equivalent circuit comprising an intrinsic diode, the cathode of the intrinsic diode connected to the drain terminal of the additional MOSFET and the anode of the intrinsic diode connected to the source terminal of the additional MOSFET. The channel of the additional MOSFET is rendered non-conductive and the second cathode terminal comprises the drain terminal of the additional MOSFET and the second anode terminal comprises the second source terminal of the additional MOSFET. The additional MOSFET may be rendered non-conductive by means of a connection between the gate control terminal of the additional MOSFET and the source terminal of the additional MOSFET.
The circuit may include a two-terminal synchronous rectifier having a MOSFET, an intrinsic diode and conductivity control circuitry.
In general, in another aspect, the invention features a power converter having a transformer and a core reset circuit for resetting the core of the transformer. The core reset circuit includes an integrated circuit having a semiconductor die having a MOSFET comprising a channel between a drain terminal and a source terminal and a gate control terminal for controlling the conductivity of said channel, and a diod

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