Capacitive coupled driver circuit

Details Capacitive coupled driver circuit Capacitive coupled driver circuit

1999-03-09

2001-04-10

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Signal transmission integrity or spurious noise override

Reexamination Certificate

active

06215349

ABSTRACT:

FIELD OF THE INVENTION
This disclosure relates to semiconductor devices. More particularly, the disclosure relates to a driver circuit that enables high frequency operation.
BACKGROUND OF THE INVENTION
Due to higher frequencies at which semiconductor integrated circuits (ICs) operate, IC designers are confronted with smaller or tighter operating windows. For example, in memory ICs such as dynamic random access memories (DRAMs), it is becoming more difficult to perform certain operations such as reads, writes, or precharges within a chip's cycle time. An aspect that limits the speed of operations in memory ICs is the charging of bus lines. For example, there are buses that need to be charged to an appropriate level within a clock cycle. Clocking the operation of ICs is a well-established concept. Higher operating frequencies make it increasingly difficult for a driver circuit to charge buses within the given clock cycle.
The inability of the charge circuitry to charge the buses within the given time may require a modification in the chip's operational specification. For example, a DRAM may require a wait cycle after a write operation before a read operation can be performed. However, such a solution is undesirable as it impairs performance.
A conventional technique for improving the performance of the driver is to increase the voltage to which the driver charges the load. This produces an increase in the differential or voltage swing between the logic high and logic low voltage levels. The larger voltage swing between the high and low levels requires a greater amount of time to charge and discharge, for example, the buses, causing a degradation in performance. Additionally, increasing the voltage increases the power consumption, which is undesirable, particularly with portable systems such as laptop computers.
As evidenced by the above discussion, it is desirable to provide an improved driver circuit with an increase in charge rate that allows for faster operation of ICs.
SUMMARY OF THE INVENTION
The invention relates to a driver circuit that enables high frequency operation. High frequency operation is achieved by causing the driver circuit to operate in an increased overdrive mode to increase the current flow at the output of the driver.
In accordance with the invention, an overdrive circuit is provided. The overdrive circuit increases the magnitude of the active input signal to the driver circuit, which increases the overdrive voltage applied to a driver transistor of the driver circuit. Increasing the overdrive boosts the performance of the driver transistor.
In one embodiment, the driver circuit comprises a pull-up portion to which the overdrive circuit provides an input signal. The active input signal from the overdrive circuit renders the pull-up driver transistor conductive. The overdrive circuit comprises a capacitive coupling to the input signal, creating a dynamic offset. In one embodiment, the capacitive coupling produces a dynamic offset having a peak magnitude of about 0.2-1.5 V, preferably about 0.2-1.0 V. The offset increases the magnitude of the gate overdrive voltage of the pull-up transistor, boosting the performance of the pull-up driver portion. The driver circuit can also comprise a pull-down portion. A dynamic offset via a capacitive coupling can also be applied to the input signal of the pull-down driver transistor in order to boost its performance.
In one embodiment, the pull-up portion of the driver comprises a p-FET. The overdrive circuit switches on or renders the driver transistor conductive by providing an active input signal which is negative with respect to ground. The overdrive circuitry provides a negative dynamic offset having a peak magnitude of about −0.2 to −1.5 V and preferably about −0.2 to −1.0 V to the active low signal to increase the magnitude of the gate overdrive voltage. In one embodiment, the negative dynamic offset causes the active low signal to be negative with a peak magnitude of about −0.2 to −1.5 V, preferably −0.2 to −1.0 V.
In another embodiment, the overdrive circuit provides, by using capacitive coupling techniques, an input to a pull-down portion of the driver circuit comprising an n-FET. The capacitive coupling provides a dynamic offset which increases the magnitude of the gate overdrive voltage applied to the pull-down transistor. In one embodiment, the capacitive coupling produces a dynamic offset having a peak magnitude of about 0.2-1.5 V, preferably about 0.2-1.0 V. The dynamic offset increases the active high input signal to the pull-down transistor by about 0.2-0.5 V and preferably about 0.1-1.0 V in order to increase the gate overdrive voltage, boosting the driver performance.


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