Semiconductor memory device having voltage down convertor...

Details Semiconductor memory device having voltage down convertor... Semiconductor memory device having voltage down convertor...

2000-03-31

2001-07-17

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S233100

Reexamination Certificate

active

06262931

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically, it relates to a semiconductor memory device including a power supply voltage generation circuit shared by banks.
2. Description of the Background Art
An external power supply potential ext.Vdd supplied to a semiconductor chip is increasingly reduced in response to requirement for low power consumption in a system using the semiconductor chip, for example. In practice, however, it is problematic to employ the reduced external power supply potential ext.Vdd as an operating power supply potential for a transistor provided in the semiconductor chip as such, in consideration of reliability. Therefore, an internal power supply potential Vdd lower than the external power supply potential ext.Vdd is generally generated in the chip and used as the operating power supply potential for the transistor.
FIG. 18
is a block diagram showing the structure of a synchronous dynamic random access memory (SDRAM
501
) as an exemplary conventional semiconductor chip.
Referring to
FIG. 18
, the SDRAM
501
includes four banks
0
to
3
, having a storage capacity of 256 megabits in total, capable of operating independently of each other. The SDRAM
501
performs read/write operations in synchronization with an externally supplied clock signal CLK. In order to perform a desired operation, a command decided by a combination of control signals /RAS, /CAS and /WE is supplied. A control signal /CS instructing selection of any chip, a control signal CKE instructing whether or not to capture the clock signal CLK and the like are also properly supplied from an external device.
The SDRAM
501
further includes a power supply potential generation circuit
510
receiving and stepping down an external power supply potential ext.Vdd for outputting an internal power supply potential Vdd. The power supply potential generation circuit
510
indudes a VDC control circuit
532
receiving a row activation signal from each of row decoders & word drivers
10
#
0
to
10
#
3
provided in correspondence to memory array banks
14
#
0
to
14
#
3
respectively and outputting a signal PWRUP, a Vref generation circuit
534
generating a reference potential Vref, and a VDC (voltage down convertor)
536
receiving the reference potential Vref and stepping down the external power supply potential ext.Vdd to the same level as the reference potential Vref at a response speed responsive to the signal PWRUP for outputting the power supply potential Vdd.
FIG. 19
is an operation waveform diagram showing waveforms of external signals in a write operation of the SDRAM
501
.
Referring to
FIG. 19
, the waveforms show operations with reference to a RAS-CAS delay time tRCD and a row precharge time tRP of three cycles and a burst length BL of 4.
At a time t
1
, a command ACT[
0
] for activating a row system of the bank
0
is input on the leading edge of the clock signal CLK. Each command is input with a bank address denoted by a bracketed numeral.
At the same time, a row address X for selecting a single word line WL is supplied as a combination of signals A
0
to A
12
and the bank address designating the bank
0
is supplied as a combination of signals BA
0
and BA
1
.
On the leading edge of the clock signal CLK at a time t
4
after three cycles, a command WRITE[
0
] for performing a write operation on the already activated word line WL is input. At the same time, a column address Y is supplied as a combination of the signals A
0
to A
9
, and the bank address is also supplied. The command WRITE is decided by a combination of control signals ICS, /RAS, /CAS and /WE. In four cycles from the time t
4
to a time t
7
, write data D
0
to D
3
are externally supplied by a combination of signals DQ
0
to DQ
15
and written in a memory cell.
At a time t
8
, a command PRE[
0
] for resetting the word line WL of the active bank
0
is input. The command PRE is supplied by a combination of he control signals /CS, /RAS, /CAS and /WE. After the final data D
3
is written, a time tWR must be set before the command PRE[
0
] is input, in order to guarantee that the data are reliably written in the memory cell. Data can be written in a specific bank in the aforementioned manner.
When continuously accessing the same bank
0
, a time exceeding a row precharge time tRP must be set before inputting the next command ACT[
0
].
A representative specification of such an SDRAM is referred to as “PC 100”, and the following description is made with reference to the SDRAM
501
based on PC
100
.
When performing the operations shown in
FIG. 19
, current consumption in the SDRAM
501
temporally changes under the internal power supply potential Vdd.
FIG. 20
is a schematic waveform diagram showing temporal change of current consumption.
Referring to
FIG. 20
, current consumption starting from each command input abruptly increases under the power supply potential Vdd in a single row cycle, i.e., a cycle for executing the commands ACT, WRITE and PRE. The SDRAM
501
performing a read/write operation at a high speed exhibits extremely large peak and average values of current consumption. On the other hand, the SDRAM
501
exhibits small current consumption in periods between the times t
2
and t
3
and between the times t
4
and t
5
, i.e., periods Trs
1
and Trs
2
after completing prescribed operations and before receiving next commands. In general, the period Trs
1
or Trs
2
is referred to as an active standby period, which is different from the so-called standby period when no row system is activated. A current Ias consumed in the active standby state is larger than a current Iss consumed in the standby state due to activation of the row system. In order to cope with such fluctuation of current consumption under the power supply potential Vdd, the VDC (voltage down convertor)
536
generating the power supply potential Vdd must be properly controlled.
The VDC
536
shown in
FIG. 18
is formed by a comparator and a driver, as described later with reference to embodiments of the present invention. The operating speed of the comparator increases in response to a through current Ic flowing therein, while this through current Ic is preferably reduced in the standby period or the active standby period. Therefore, the VDC control circuit
532
changes the signal PWRUP output therefrom in response to a current consumed in a power source for switching the value of the through current Ic.
FIG. 21
is a diagram for illustrating the structure of the VDC control circuit
532
shown in FIG.
18
.
Referring to
FIGS. 18 and 21
, a control circuit & mode register
8
shown in
FIG. 18
includes a bank address decoder
92
, a command decoder
94
and a selection circuit
96
. The bank address decoder
92
receives internal bank address signals int.BA
0
and int.BA
1
from an address buffer
2
, decodes the same and outputs bank designation signals BAD
0
to BAD
3
. Each prefix “int.” indicates that the signal is obtained by latching an externally supplied signal in a high-level period of an internal clock signal CLKI.
The command decoder
94
receives control signals int.RAS, int.CAS and int.WE from a control signal input buffer
6
, decodes the same and outputs a signal ACTF indicating input of an ACT command and a signal PREF indicating input of a PRE command. The signals ACTF and PREF are generated irrelevantly to bank information. The selection circuit
96
receives the bank designation signals BAD
0
to BAD
3
and the signals ACTF and PREF. The selection circuit
96
generates signals ACTF
0
to ACTF
3
activating row systems of the banks
0
to
3
and signals PCGF
0
to PCGF
3
inactivating the row systems of the banks
0
to
3
. These signals ACTF
0
to ACTF
3
and PCGF
0
to PCGF
3
go high only by one cycle in the designated banks
0
to
3
.
These signals ACTF
0
to ACTF
3
and PCGF
0
to PCGF
3
are input in latches
100
#
0
to
100
#
3
provided in

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