Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1999-11-12
2001-04-17
Niebling, John F. (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S759000, C257S760000
Reexamination Certificate
active
06218735
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor manufacturing processes, and more particularly to techniques for improving the adhesion of a cap layer to an underlayer that includes methyl doped silicon oxide material that is vapor deposited.
2. Description of the Related Art
As semiconductor manufacturing technology produces devices that are faster and more efficient, both the density of conductive lines and the frequency of charges flowing on the conductive lines tend to increase. Because semiconductors rely on insulating (i.e. dielectric) layers to reduce capacitive coupling between the conductive lines, it has become increasingly important to have insulation that is able to accommodate both the higher operating frequencies and the shrinking distances between the lines.
FIG. 1A
is a cross-sectional view illustrating the respective layers of a typical semiconductor structure
10
. The semiconductor structure
10
is made up of several layers including a cap layer
12
, a dielectric SiO
2
layer
14
, and a semiconductor substrate
16
. The semiconductor substrate
16
typically supports a first metal layer
18
formed into a number of conductive traces
18
a,
18
b,
18
c
and
18
d.
A second metal layer
22
including traces
22
a
and
22
b
may be provided over the cap layer
12
. A number of conductive vias, such as conductive via
20
, are provided through the dielectric SiO
2
layer
14
and the cap layer
12
, connecting the traces of metal layer
18
to traces of metal layer
22
. For ease of illustration, only one conductive via
20
and six metal traces
18
a-d
and
22
a-b
are shown, but as is well known in the art, many more conductive vias and metal traces are used to provide appropriate connections in a semiconductor or integrated circuit device.
A first plurality of capacitive couplings
26
exist between the first metal layer
18
and the second metal layer
22
. A second plurality of capacitive couplings
28
exist between the metal traces
18
a-d.
The purpose of the dielectric SiO
2
layer
14
is to insulate the metal traces and to reduce capacitive couplings
26
and
28
.
With higher line density and higher operating frequencies, the coupling capacitances
26
and
28
are increasing to the point that dielectric SiO
2
layer
14
is a less than adequate insulator. Raising the operating frequency requires a reduction in both the first coupling capacitance
26
and the second coupling capacitance
28
. Furthermore, increasing the densities of the metal traces
18
a-d
decreases the distance d
1
between each of the metal traces
18
a-d
which further increases the second capacitive coupling
28
.
Another important dimension in
FIG. 1A
is the thickness t
1
of the dielectric SiO
2
layer
14
. If the insulating material can be made thicker, the first coupling capacitance
26
can be reduced. Unfortunately, the dielectric SiO
2
layer
14
may have only a maximum thickness t
1
of about 3,000 Angstroms. If the dielectric layer thickness t
1
exceeds 3,000 Angstroms, the dielectric SiO
2
layer
14
will begin to crack and form rifts
30
. Therefore, semiconductors need an alternative material that is both a better insulator (having a lower dielectric constant) and which resists cracking.
As illustrated in
FIG. 1B
, one way for improving the insulation of the semiconductor structure is to add methyl groups to the standard dielectric SiO
2
layer
14
in
FIG. 1A
to produce a methyl doped silicon oxide layer
34
. Adding methyl groups lowers the dielectric constant of the methyl doped silicon oxide layer
34
to about 2.8. The methyl groups, which are added with a solvent free operation allows a thickness t
2
greater than 3,000 Angstroms (typically up to 10,000 Angstroms) without cracking.
Unfortunately, adding methyl groups to the dielectric layer can also cause the cap layer
12
, which is added to protect the semiconductor structure, to peel away (as illustrated) during a subsequent chemical mechanical polishing (CMP) process used to planarize the cap layer. This is because the cap layer
12
doesn't adhere well to the methyl doped silicon oxide layer
34
.
In view of the foregoing, it is desirable to have a method that provides for a low dielectric constant, low-cracking insulating material that adheres well to the cap layer all in the same semiconductor apparatus without adding significant time or cost to the process.
SUMMARY OF THE INVENTION
The present invention fills these needs by providing an efficient and economical method for improving adhesion of a cap oxide to a methyl doped silicon oxide material. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device or a method. Several inventive embodiments of the present invention are described below.
In one embodiment, a method for making a multi-layered integrated circuit structure is disclosed. This method includes: (a) depositing a methyl doped silicon oxide layer with a first thickness over a substrate under a first set of conditions; (b) depositing a SiO
2
skin with a second thickness on the methyl doped silicon oxide layer under a second set of conditions wherein the second thickness is substantially thinner than said :first thickness; and (c) depositing a cap layer adhering on the SiO
2
skin under a third set of conditions. The methyl doped silicon oxide is preferably CH
3
SiO
x
. In addition, the depositions are preferably performed in a same semiconductor apparatus.
In another embodiment, a method for making a multi-layered integrated circuit structure is disclosed. This method includes a second set of conditions comprising: (a) flowing CH
3
SiH
3
into a semiconductor apparatus wherein the volume of CH
3
SiH
3
is decreased over a period of time; (b) flowing SiH
4
into a semiconductor apparatus wherein the volume of SiH
4
is increased over said period of time; and (c) flowing H
2
O
2
into the semiconductor apparatus wherein the volume of H
2
O
2
is held constant over a period of time to produce a SiO
2
skin over the methyl doped silicon oxide layer. The period of time is preferably in the range of about 10-20 seconds.
An advantage of the present invention is that it improves adhesion between a methyl doped silicon oxide layer and a cap layer. Methyl doped silicon oxide material is an improvement over a standard dielectric material because it has a lower dielectric constant. Furthermore, methyl doped silicon oxide material can also be made much thicker than normal dielectric material because it resists cracking. Both of these factors allow the methyl doped silicon oxide layer to reduce inter-metal capacitance in the integrated circuit.
An additional advantage of the present invention is that it improves the adhesion of the methyl doped silicon oxide layer and the cap layer with minimal additional procedures, time and expense. Formation of the SiO
2
skin can be accomplished using the same semiconductor apparatus that is used to deposit both the methyl doped silicon oxide layer and the cap layer.
Therefore, the process of the present invention reduces the chance for contamination of the semiconductor wafer over a procedure that requires removal of the wafer from the semiconductor apparatus. Furthermore, the process of the present invention requires minimal additional cost and time because it can be completed in a few seconds between methyl doped silicon oxide layer and cap layer deposition.
Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
REFERENCES:
patent: 5716890 (1998-02-01), Yao
patent: 5821621 (1998-10-01), Jeng
patent: 5872065 (1999-02-01), Sivaramakrishnan
patent: 5879574 (1999-04-01), Sivaramakrishnan et al.
patent: 5955787 (1999-09-01), Yu et al.
patent: 5994778 (1999-11-01), Huang et al.
patent: 6001747 (1999-12-01), Annapragada
patent: 6124
Gurley Lynne A.
Niebling John F.
Oppenheimer Wolff & Donnelly LLP
Philips Semiconductor Inc.
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