Television – Camera – system and detail – Solid-state image sensor
Reexamination Certificate
1995-11-08
2001-09-11
Garber, Wendy (Department: 2712)
Television
Camera, system and detail
Solid-state image sensor
C348S317000, C348S319000, C348S322000
Reexamination Certificate
active
06288744
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a two-dimensional solid-state image pickup device in which a plurality of pixels are arranged in the shape of a matrix, and a method of driving such a solid-state image pickup device.
2. Description of the Related Art
A solid-state image pickup device, a so-called area sensor, is used for an imaging apparatus such as a video camera, and includes a plurality of pixels arranged in the shape of a matrix. The solid-state image pickup device reads out information charges indicative of information, produced by respective pixels through photoelectric conversion, in a predetermined order via a plurality of shift registers.
Referring to
FIG. 1
of the accompanying drawings, a frame transfer type CCD solid-state image pickup device comprises a plurality of juxtaposed vertical shift registers
1
and a horizontal shift register
2
. Each of the vertical shift registers
1
includes an image pick-up section and a storage section which are aligned. The horizontal shift register
2
is located at output sides of the respective vertical shift registers
1
.
Each image pick-up section includes a plurality of pixels formed by electrically dividing each shift register
1
. In response to a frame transfer clock pulse FS, information charges produced by the pixels are transferred from the image pick-up section to the storage section, where the information charges are temporarily stored. Then, in response to a vertical transfer clock pulse VS, the stored information charges are transferred line by line to each bit of the horizontal shift register
2
. In accordance with a horizontal transfer clock pulse HS, each line of the information charges is transferred from the horizontal shift register
2
to an output unit
3
. The output unit
3
converts an amount of the information charges into a voltage value, which is transmitted as a picture signal.
An interline type CCD solid-state image pickup device, shown in
FIG. 2
, comprises a plurality of pixels
4
arranged in an array, a plurality of vertical shift registers
5
interposed between columns of the pixels
4
, and a horizontal shift register
6
located at output sides of the vertical shift registers
5
.
Information charges present at the pixels are transferred to the vertical shift register
5
, from which they are transferred, line by line, to the horizontal shift register
6
in response to a vertical transfer clock pulse VS. As with the frame transfer type CCD solid-state image pickup device, the information charges are transferred line by line from the horizontal shift register
6
to an output unit
7
. Then, the output unit
3
transmits the information charges as a picture signal.
FIG. 3
shows a manner in which the vertical and horizontal shift registers are interconnected in the CCD solid-state image pickup device of the prior art.
The solid-state image pickup device comprises a plurality of vertical shift registers
10
. Each vertical shift register
10
includes a channel region
11
and a plurality of transfer gate electrodes
12
,
13
which are arranged in an overlapping manner. The channel regions
11
and the transfer gate electrodes
12
,
13
are formed on a semiconductor substrate. The transfer gate electrodes
12
,
13
are commonly used for the shift registers
10
. The channel regions
11
are separated by channel-stop regions
14
made of insulators such as thick oxide layers which are selectively oxidized, and are electrically independent from one another. Each channel region
11
is a buried channel in which an N-type region is implanted on a P-type region. The transfer gate electrodes
12
are disposed on and across the channel region
11
and the channel-stop region
14
, and are equally spaced therebetween. The transfer gate electrodes
13
are disposed on the channel region
11
between the transfer gate electrodes
12
in such a manner as to overlap with the transfer gate electrodes
12
. Four-phase vertical transfer clock pulses VS
1
to VS
4
are applied to the transfer gate electrodes
12
,
13
. Thus, information charges are vertically and sequentially transferred from the channel regions
11
in response to the vertical transfer clock pulses VS
1
to VS
4
.
A horizontal shift register
20
includes a channel region
21
and a plurality of transfer gate electrodes
22
and
23
. The channel region
21
is defined by an insular channel-stop region
24
extending from the channel-stop region
14
of the vertical shift registers
10
and a channel-stop region
25
positioned opposite to the insular channel-stop region
24
. The channel region
21
is connected to ends of the channel regions
11
of the vertical shift registers
10
via spaces between the insular channel separators
24
. The channel region
21
is a buried channel similar to the channel region
11
. The gate transfer electrodes
22
span across the channel-stop regions
24
,
25
. Further, every two transfer gates
22
extend to the shift registers
11
, cover connecting portions between the channel regions
11
of the vertical shift registers
10
and the channel regions
21
, and overlap with the transfer gate electrodes
13
at the output ends of the vertical shift registers
10
. The transfer gate electrodes
23
are disposed above the channel region
21
such that they cover the spaces between the transfer gate electrodes
22
. The transfer gate electrodes
22
,
23
overlap with one another. Every two adjacent transfer gate electrodes
22
,
23
are interconnected.
Two-phase horizontal clock pulses HS1, HS2 are applied to each connected pair of transfer gate electrodes
22
,
23
. In response to the horizontal clock pulses HS1, HS2, the information charges in the channel regions
21
are horizontally transferred. The horizontal transfer clock pulses HS1, HS2 are set such that one line of the information charges is transferred while the information charges in the vertical shift register
10
are transferred to each next bit in response to the vertical transfer clock pulses VS1 to VS4. Therefore, the information charges transferred to the horizontal shift register
20
from the vertical shift register
10
are transmitted outside the horizontal shift register
20
before the vertical shift register
10
transfer succeeding information charges to the horizontal shift register
20
.
In the foregoing CCD solid-state image pickup device, a total of four electrodes, i.e. two transfer gate electrodes
22
and two transfer gate electrodes
23
, should be arranged in each vertical shift register. Therefore, it is impossible to make a pitch of each vertical shift register
10
smaller than a minimum space for housing the transfer gate electrodes
22
,
23
. It is therefore necessary to enlarge the CCD solid-state Image pickup device so as to improve resolution of the Image pickup device by increasing the number of pixels. This measure inevitably makes the image pickup device expensive.
SUMMARY OF THE INVENTION
It is an object of the present invention to simplify the structure of the connecting parts between the vertical shift registers and the horizontal shift register, and to enhance integration of elements by reducing the pitch of the vertical shift registers.
According a first aspect of the invention, there is provided a solid-state image pickup device comprising: a plurality of vertical shift registers for vertically transferring the information charges generated by a plurality of pixels, the vertical shift registers corresponding to respective columns of the pixels; a horizontal shift register for receiving the information charges from an end of the plurality of vertical shift registers and horizontally transferring the information charges; and an output unit for converting the information charges from one end of the horizontal shift register into a voltage value and generating a picture signal. The vertical shift registers includes a group of vertical transfer electrodes for vertically transferring the information charges in each column and at least two output-con
Takahashi Hideki
Watanabe Tohru
Garber Wendy
Hogan & Hartson L.L.P.
Moe Aung S.
Sanyo Electric Co,. Ltd.
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