Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1997-06-11
2001-08-07
Brown, Glenn W. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S538000, C324S133000, C235S438000
Reexamination Certificate
active
06271675
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a contact-type IC card that functions when its terminals are in contact with the terminals of an external unit. The present invention also relates to an IC card system employing an IC card and to an integrated circuit (IC) used for IC cards. In particular, the present invention relates to a contact-type IC card capable of detecting contact fault on terminals and coping with the contact fault, and to an IC card system employing such an IC card.
2. Description of the Prior Art
IC cards generally have a plastic package and incorporate IC chips such as a microcomputer chip and a memory chip. Among the IC cards, a contact-type IC card has metal terminals that are brought in mutual contact with the terminals of a reader-writer, to communicate data between them.
FIG. 1
shows a conventional IC card system employing a contact-type IC card. The IC card
100
is attached to and ejected from a reader-writer
30
, which is connected to a host computer (not shown). The reader-writer
30
mediates between the IC card
100
and the host computer.
The IC card
100
has metal terminals
11
to
15
, which are brought in contact with terminals
31
to
35
of the reader-writer
30
. The IC card
100
incorporates a single semiconductor IC chip containing a CPU
106
and an EEPROM
17
. The CPU
106
controls an interface with the reader-writer
30
through the terminals
11
to
15
and an access to the EEPROM
17
. The reader-writer
30
has a control circuit
40
that controls the reception and ejection of the IC card
100
and data communication with the IC card
100
and with the host computer. Among the terminals
31
to
35
of the reader-writer
30
, the terminal
31
applies a supply voltage VDD to the IC card
100
, the terminal
32
is for grounding, the terminal
33
sends a clock signal CLK to the IC card
100
, the terminal
34
is an I/
0
terminal for data communication with the IC card
100
, and the terminal
35
sends a reset signal RST to the IC card
100
.
The contact-type IC cards are simpler in structure than non-contact-type IC cards. The contact-type IC cards, however, may cause contact failure at terminals due to, for example, dirt when repeatedly attached to and removed from a reader-writer. If contact at terminals is poor or faulty, the reader-writer is unable to control the IC card and will erroneously write or read data to or from the IC card, thereby degrading the reliability of the IC card. To solve this problem, the contact-type IC cards must have functions of detecting contact fault on terminals and coping with the same.
FIG. 2
shows a semiconductor IC for detecting an open state between terminals. This is disclosed in Japanese Unexamined Patent Publication No. 60-65621 (JP6065621).
The IC
210
has a set
220
of input terminals, a set
230
of output terminals, a sequential circuit
240
, and a gate circuit
250
for detecting an open state of the input terminal
221
. The sequential circuit
240
usually operates with the input terminals
221
and
222
. If the input terminal
221
is open, the gate circuit
250
detects the same and forcibly sets the sequential circuit
240
to a given state to provide a given value.
As soon as the gate circuit
250
detects an open state of the terminal
221
, the sequential circuit
240
is set to the given state. When applied to a contact-type IC card, the semiconductor IC disclosed in JP60-65621 quickly stops a CPU in the IC card upon detecting contact fault on, for example, a reset terminal. Then, the IC card is unable to inform a reader-writer of the fault, and the reader-writer is unable to properly and quickly cope with the fault. If such fault occurs at a clock terminal while data is being written into an EEPROM of the IC card, the data will not completely be written, or erroneous data will be stored in the EEPROM. If such fault occurs at the clock terminal while data is being read out of the EEPROM, the data will not completely be read, or erroneous data will be read. In this way, the semiconductor IC disclosed in above JP60-65621 cannot cope with the contact fault and is incapable of improving the reliability of IC cards.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor IC for a contact-type IC card, capable of quickly coping with contact fault occurring on a terminal of the IC card.
Another object of the present invention is to provide a semiconductor IC incorporated in an IC card, having a simple structure to test a contact condition between the terminals of the IC card and the terminals of an external unit.
Still another object of the present invention is to provide an IC card having a simple structure to surely detect contact fault between a reset terminal of the IC card and a corresponding terminal of an external unit and quickly and properly cope with the contact fault.
Still another object of the present invention is to provide an IC card having a simple structure to surely detect a poor contact between a clock terminal of the IC card and a corresponding terminal of an external unit and quickly and properly cope with the poor contact.
Still another object of the present invention is to provide an IC card capable of correctly writing data even if contact fault occurs during a write operation.
Still another object of the present invention is to provide an IC card capable of easily identifying erroneous data written on contact fault.
Still another object of the present invention is to provide an IC card capable of correctly reading data even if contact fault occurs during a read operation.
Still another object of the present invention is to provide an IC card system having a simple structure to surely detect a poor contact between a reset terminal of an IC card and a corresponding terminal of an external unit such as a reader-writer, and capable of properly and quickly coping with the poor contact.
Still another object of the present invention is to provide an IC card system having a simple structure to surely detect contact fault between a clock terminal of an IC card and a corresponding terminal of an external unit such as a reader-writer, and capable of properly and quickly coping with the contact fault.
Still another object of the present invention is to provide an IC card system capable of correctly writing data even if contact fault occurs during a write operation.
Still another object of the present invention is to provide an IC card system capable of easily identifying erroneous data written on contact fault.
Still another object of the present invention is to provide an IC card system capable of correctly reading data even if contact fault occurs during a read operation.
In order to accomplish the objects, a first aspect of the present invention provides a semiconductor IC for an IC card. The IC card has a first set of terminals to be connected to a second set of terminals of an external unit. The semiconductor IC embedded in the IC card has an internal circuit, detecting means such as a detector, and control means such as a controller. The internal circuit receives electric signals from the first set of terminals. The detecting means detects a poor contact, or a contact fault between the first and second sets of terminals. The controlling means controls the internal circuit according to the output of the detector. The detecting means is connected to a reset terminal among the first set of terminals through a line. A terminal among the second set of terminals corresponding to the reset terminal is connected to a pull-up resistor. Namely, the pull-up resistor is connected between a high-level power supply and the terminal corresponding to the reset terminal. The detecting means includes first and second transistors. The first transistor is arranged between and connected to the high-level power supply and the reset terminal. The second transistor is arranged between and connected to the reset terminal and a low-level power supply such as ground (GND). The second transistor h
Brown Glenn W.
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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