Static information storage and retrieval – Powering – Conservation of power
Reexamination Certificate
2000-12-05
2001-08-14
Mai, Son (Department: 2818)
Static information storage and retrieval
Powering
Conservation of power
C365S226000
Reexamination Certificate
active
06275440
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and a method of operating it, and principally to a technique effective for use in a digital integrated circuit device such as a dynamic RAM (Random Access Memory) comprising CMOS circuits each composed of low threshold-voltage type MOSFETs and in a method of operating the digital integrated circuit device.
MOSFETs experience reduced withstand voltage with increased micronization. It is therefore necessary to reduce the operating voltage of a circuit composed of the MOSFETs shaped in micro form. Since a gate voltage supplied to the gate of each MOSFET is also lowered in this case, it is necessary to reduce the threshold voltage of the MOSFET so that even the lowered gate voltage provides for flow of a desired current. However, when the threshold voltage is reduced, a leakage current (hereinafter called a “subthreshold leakage current”), which flows when each MOSFET is brought into an off state, in which the gate and source thereof are equal in voltage to each other, increases exponentially. Thus, even in the case of a CMOS circuit, current consumption at the time of its deactivation increases.
A circuit for reducing the subthreshold leakage current referred to above has been disclosed in Japanese Patent Application Laid-Open Nos. 6(1994)-237164 and 8(1996)-83487 and U.S. Pat Nos. 5,274,601 and 5,408,144 by way of illustrative example. As a method of reducing the leakage current using such a circuit, a CMOS inverter circuit wherein, at the time that an input thereof received its non-operation and an output thereof have been determined as a high level and a low level, respectively, will be described by way of example. In this case, a P channel MOSFET of the CMOS inverter circuit is in an off state and an N channel MOSFET thereof is in an on state. A leakage current produced in the CMOS inverter circuit is determined depending on the subthreshold leakage current of the turned-off P channel MOSFET.
A P channel power switch MOSFET is provided between an operating voltage node connected to the source of the P channel MOSFET of the CMOS inverter circuit and a power line and is turned off upon non-operation. In doing so, the potential at each internal power line placed in a floating state is reduced by the subthreshold leakage current. When the potential is reduced to a some extent, a reverse bias voltage is applied between the gate and source of the P channel MOSFET of the CMOS circuit so that the subthreshold leakage current can be substantially eliminated.
SUMMARY OF THE INVENTION
The inventors of the present application have discussed the application of a method of reducing a subthreshold leakage current to a dynamic RAM. In this case, the present inventors have found out various problems which need to be solved without sacrificing the operating speed of the dynamic RAM and to effectively reduce the subthreshold leakage current. Namely, an internal power switch MOSFET is turned off upon standby to reduce the subthreshold leakage current and is turned on upon memory access. In doing so, a pulse-shaped large current will flow when a control signal for changing such a MOSFET from the off state to the on state rises and the power node of the internal circuit is charged up in response to the turning on of the MOSFET. This pulsating current will increase the value of the peak current of a semiconductor integrated circuit device. Upon mounting of such a system, the current capacity of the power device must be increased so as to correspond to the peak value.
The increase in the circuit function and circuit scale of the semiconductor integrated circuit device and the reduction in its source voltage with the device micronization as described above tends toward a size reduction of a system including the device, such as a portable electronic device or the like. A battery is also expected to be inevitably used as the power supply. However, the increase in peak current offers a large problem as viewed from the power device of the system, which needs its size reduced. Even in the case of the semiconductor integrated circuit device, large noise is produced in the power line with the occurrence of the peak current referred to above, and hence the operating margin thereof is made worse.
An object of the present invention is to provide a semiconductor integrated circuit device which is capable of realizing less power consumption while ensuring its operating margin. Another object of the present invention is to provide a semiconductor integrated circuit device capable of realizing high integration, a voltage reduction and less power consumption without sacrificing its operating speed.
The above and other objects, novel features and advantages of the present invention will become apparent from the following description and the appended claims of the present specification, taken in conjunction with the accompanying drawings in which preferred embodiments of the present invention are shown by way of illustrative example.
A summary of a typical one of the inventive features disclosed in the present application will be described in brief as follows. A plurality of switch MOSFETs are provided in parallel between internal power lines for a plurality of circuit blocks divided for respective functions and respectively set so as to perform circuit operations in response to operation control signals and a power line for delivering an operating voltage supplied from an external terminal. These switch MOSFETs are turned on in domino or stepwise fashion in response to control signals produced by successively delaying the operation control signals, so as to provide the supply of operating voltages.
A summary of another typical one of the inventive features disclosed in the present application will be described in brief as follows. A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon reaching its non-operating state. Further, the switch MOSFETs are turned on in domino or stepwise fashion in response to control signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.
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Aoki Masakazu
Horiguchi Masashi
Idei Youji
Itoh Kiyoo
Kajigaya Kazuhiko
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Mai Son
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