Offset digitally controlled oscillator

Details Offset digitally controlled oscillator Offset digitally controlled oscillator

1986-10-09

1987-12-08

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Having phase shift

377 39, 377 47, 328 63, 331 1A, H04L 702, H03L 718

Patent

active

047122242

ABSTRACT:
An all digital equivalent to a voltage controlled oscillator with low intrinsic jitter and the absence of sample aliasing within a nonzero bandwidth, the offset (non-symmetrical) digitally controlled oscillator comprising a divider (divide by n or n-1) which is timed from a high speed reference clock, a 2.sup.m counter and a digital comparator. The divider divides the high speed reference clock signal so that for every thirty second cycle of the high speed reference clock a pulse is output from the present invention. The output pulse is input to the 2.sup.m counter and increments same. The 2.sup.m counter counts the number of output cycles (or pulses) that have occurred since the last phase adjustment and comares this m-bit number to the input to the present invention. When the output of the 2.sup.m counter becomes greater than or equal to the input, a divide by n-1 signal is sent to the divider which shortens the output cycle and adjusts the average output frequency and phase. The 2.sup.m counter is reset to a value of zero each time a divide by n-1 occurs.

REFERENCES:
patent: 3662330 (1972-05-01), Meredith
patent: 3959737 (1976-05-01), Tanis
patent: 4184068 (1980-01-01), Washburn
patent: 4423381 (1983-12-01), Stepp et al.
patent: 4468797 (1984-08-01), Shin

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