Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-08-07
2001-07-17
Nguyen, Vinh P. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S760020
Reexamination Certificate
active
06262588
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
This invention applies to semiconductor testing and in particular to burn-in testing and the monitoring of product bias during burn-in.
2. Description of Related Art
Burn-in testing is an important means by which infant mortality and early life failures can be culled out from a semiconductor product line. At the same time it is important that the product be tested under bias stress during burn-in. The stress testing should not be to much leading to unnecessary failures or too little and not finding enough failing parts to assure an outgoing product quality level.
The applied bias to the semiconductor parts during burn-in provides the necessary electrical stress and is usually at a voltage higher than for normal operations. Shifts in this voltage, commonly called “noise”, provides a source of the product being over stressed or under stressed during test. This potential for bias voltage variation as seen by the product under test gives rise to the need for a means to monitor the applied voltage.
In U.S. Pat. No. 5,452,253 (Choi) an internal voltage generator provides a regulated bias for a semiconductor memory array. When a burn-in stress voltage is detected, the internal voltage generator provides an voltage stress to the semiconductor array. The burn-in test mode is activated if particular signal conditions are met and the external voltage is higher than a pre-set burn-in test voltage. This prevents the test device from entering test mode due to noise on the external power supply.
IN U.S. Pat. No. 5,561,639 (Lee et al.) a burn-in test signal generator detects whether the applied voltage bias to a semiconductor memory chip is normal or at a burn-in level. When a burn-in level voltage is detected, test time can be reduced by selecting a plural of memory cell rows in accordance with any address applied during burn-in and different from normal operations.
In U.S. Pat. No. 5,656,944 (Choi) a burn-in detection circuit detects whether an external applied voltage is above a predetermined voltage level for burn-in testing and having a hysteresis effect in which coming out of burn-in test is not allowed until the applied external voltage further increases before decreasing. This in turn prevents noise on the external voltage from taking the test device out of burn-in.
Whereas, the above references concentrate on providing a burn-in bias and attempting to avoid noise on the applied external voltage bias, it is important to know what the external voltage bias is throughout the burn-in test. Determining that the voltage bias that is stressing the product is too high could indicate that there were parts that failed which should have passed the test. At the same time an under voltage provides an under stress of the product and could provide tested parts that have too high a failure rate.
SUMMARY OF THE INVENTION
It is an objective of this invention to provide a means for tracking and measuring the bias voltage in situ during burn-in to determine whether the voltage stress of the product under test was within defined limits during test. To accomplish this an EPROM, particularly configured, is connected to the voltage bias on the test board and monitors the bias applied to the product during, burn-in.
The use of the EPROM with a P-type substrate to measure the applied voltage works on the threshold voltage shift mechanism. The gates of the EPROM induce electrons at the substrate surface and the drain will accelerate the electron energy. Once these electrons exceed the gate oxide energy barrier, they become trapped into the polysilicon gate. This in turn shifts the gate threshold voltage. Over time for a particular voltage the threshold voltage will continue to increase. Upon calibrating the change in threshold voltage versus time for a particular voltage source, the change in threshold voltage for an amount of elapsed time provides a measure of the applied voltage. This change in threshold voltage can be measure at any time during or after the test. The threshold voltage can be erased and returned to normal by applying ultra violet light to the EPROM. An EEPROM or other similarly constructed device could also be used to make the in situ voltage measurement in a similar way.
A burn-in test configuration called “board isolation” is connected with one hundred to two hundred semiconductor devices on the board with all signal pins of each device with the same pin assignment connected together and in turn connected to a driver board through a resistor. A voltage bias is connected to each semiconductor device and to an EPROM configured to monitor the voltage bias and record the maximum voltage occurrence during the burn-in test. A second burn-in test configuration known as “row isolation” is configured such that signal pins with the same pin assignment for the semiconductor devices in a row on the test board are connected together, and each row of signal pins is connected to the driver board through a separate resistor. A voltage bias is connected to each row of semiconductors devices and to an EPROM configured to monitor the voltage bias during burn-in and record the maximum voltage occurrence.
A third burn-in test configuration known as “socket isolation” is configured such that each signal pin of each semiconductor device is connected together and further connected to a driver board through a resistor. A voltage bias is connected separately to each semiconductor device, and an EPROM is connected to each voltage bias to monitor the voltage bias during burn-in and record the maximum voltage occurrence.
The voltage bias to which the EPROM's are connected induce a gate threshold voltage that is proportional to the voltage bias. As the voltage bias fluctuates to be larger than the previous voltage bias value the gate threshold voltage increases. When the voltage bias fluctuates to be less than the previous voltage bias value the gate threshold voltage remains unchanged.
The reading of the EPROM gate threshold voltage can be done after testing is complete or during the burn-in test. The threshold voltage measurement can be done during burn-in once a relay is switched from test mode to measurement mode. In test mode the relay connects the drain and the gate of the EPROM together and to V
DD
. During test mode the relay connects the gate and drain separately to a test system measurement unit so that the threshold voltage can be measured. The EPROM can be erased by using ultra violet light which will recover the threshold voltage to an initial value.
REFERENCES:
patent: 4799021 (1989-01-01), Cozzi
patent: 4900948 (1990-02-01), Hamilton
patent: 5452253 (1995-09-01), Choi
patent: 5561639 (1996-10-01), Lee et al.
patent: 5656944 (1997-08-01), Choi
patent: 5923098 (1999-07-01), Olson
Ackerman Stephen B.
Nguyen Vinh P.
Saile George O.
Vanguard International Semiconductor Corporation
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