Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2001-01-08
2001-09-18
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
active
06291268
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of testing cavity-up BGA substrate whereby an important step in the testing procedure is to define the last metal layer on the back of the metal panel by an etch or by a semi-additive plating process. The testing procedure of the invention does not require probing the high density flip chip pad array (that is flip chip bump pads and BGA pads) in order to test for defects of interconnect opens, thereby saving the cost of a sophisticated and expensive tester with tester fixtures.
(2) Description of the Prior Art
Increased packaging density of semiconductor devices has led to the design and effective use of many different types of semiconductor device packages. Multi layer structures have for this purpose been used to connect closely spaced integrated circuits with each other. Using this technique, a single substrate serves as an interconnect medium, multiple chips are connected to the interconnect medium forming a device package with high packaging density and dense chip wiring. The chip wiring contains layers of interconnect metal that are interconnected with interconnect vias, layers of dielectric (such as polyimide) or insulating layers separate metal layers that make up the interconnect network and the via and contact points that establish connections between the interconnect networks. The design of overlying and closely spaced interconnect lines is subject to strict rules of design that are aimed at improving package performance despite the high density packaging that is used. For instance, electrical interference between adjacent lines is minimized or avoided by creating interconnect lines for primary signals that intersect under 90 degree angles. Surface planarity must be maintained throughout the construction of multi-layer chip packages due to requirements of photolithography and package reliability. Many of the patterned layers within a layered structure form the base for overlying layers, lack of planarity can therefore have a multiplying effect on overlying layers.
One of the approaches that has in the past been used for high density packages that allows for the creation of high pin count integrated packages with various pin configurations is the creation of the Quad Flat Package (QFP). The pin I/O connections for these packages are typically established by closely spaced leads distributed along the four edges of the flat package. This limits the I/O count of the packages and therefore the usefulness of the QFP. The Ball Grid Array (BGA) package has been created whereby the I/O connects for the package are distributed around the periphery of the package and over the complete bottom of the package. The BGA package can therefore support more I/O points and provides a more desirable package for high circuit density with high I/O count. The BGA contact points are solder balls that in addition facilitate the process of flow soldering of the package onto a printed circuit board. The solder balls can be mounted in an array configuration and can use 40, 50 and 60 mil spacings in a regular or staggered pattern.
Where circuit density keeps increasing and device feature size continues to be reduced, the effect of the interconnect metal within the package becomes relatively more important to the package performance. Factors that have a negative impact on circuit performance, such as line resistance, parasitic capacitance, RC-delay constants, crosstalk and contact resistance have a significant impact on the package design and its limitations. A significant power drop may for instance be introduced along the power and ground buses where the reduction of the interconnect metal does not match the reduction in device features. Low resistance metals (such as copper) are therefore finding wider application in the design of dense semiconductor packages.
Increased I/O combined with increased performance requirements for high performance IC's has led to the development of Flip Chip packages. Flip chip technology fabricates bumps (typically Pb/Sn solder) on Al pads and interconnects the bumps directly to the package media, which are usually ceramic or plastic based. The flip-chip is bonded face down to the package through the shortest paths. These technologies can be applied not only to single-chip packaging but also to higher or integrated levels of packaging, in which the packages are larger, and to more sophisticated package media that accommodate several chips to form larger functional units.
The flip-chip technique, using an area array, has the advantage of achieving the highest density of interconnection to the device and a very low inductance interconnection to the package. However, pre-testability, post-bonding visual inspection, and Temperature Coefficient of Expansion (TCE) matching to avoid solder bump fatigue are still challenges. In mounting several packages together, such as surface mounting a ceramic package to a plastic board, the TCE mismatch can cause a large thermal stress on the solder lead joints that can lead to joint breakage caused by solder fatigue from temperature cycling operations.
U.S. Pat. No. 5,874,321 (Templeton Jr. et al.) shows a cavity up flip chip package and testing method. Also, shows a cavity down package FIG.
2
. However, this reference differs from the invention.
U.S. Pat. No. 5,578,869 (Hoffman et al.) shows a metal base/panel for a package.
U.S. Pat. No. 5,509,553 (Hunter, Jr. et al.) shows a metal layer process (DEMR).
FIG. 5
a
of this invention appears to comprise: a) sputter plating base, and b) plating metal (semi-additive plating). See also col. 2.
SUMMARY OF THE INVENTION
A principle objective of the invention is to provide a simple and inexpensive method for testing complex, high-density flip chip packages for electrical shorts or opens.
Another objective of the invention is to simplify the testing process that is typically required when testing complex, high-density flip chip packages for electrical shorts or opens.
Yet another objective of the invention is to eliminate the use of fixtures for chip probing, fixtures which are typically expensive, time consuming to build, unreliable and requiring frequent modifications and maintenance.
Yet another objective of the invention is to provide a method of testing complex, high-density flip chip packages for electrical shorts or opens that can be performed by visual inspection followed by simple procedures of probing for electrical shorts.
In accordance with the objectives of the invention a new method is provided for the testing of complex, high density flip chip packages. A temporary electrical short is provided by a layer of metal for all the interconnect metal lines of the package, vias are created in a surface of the package for the connection of the flip chips to the package. These vias are plated using either copper or tin or copper followed by nickel followed by gold. The process of plating requires uninterrupted electrical paths between the vias that are being plated through the interconnect lines, which are being tested, to the layer of metal that provides a temporary electrical short. Where this uninterrupted electrical path is not present, due to problems of poor via creation or problems of opens in the interconnect lines of the package, the vias will not be plated and can as a result be readily identified by visual inspection. The metal layer that has provided the common short between all interconnect lines of the package is now patterned, probed and inspected for problems of shorts or opens.
REFERENCES:
patent: 5509553 (1996-04-01), Hunter, Jr. et al.
patent: 5578869 (1996-11-01), Hoffman et al.
patent: 5874321 (1999-02-01), Templeton, Jr. et al.
patent: 6221693 (2001-04-01), Ho
Ackerman Stephen B.
Hoang Quoc
Nelms David
Saile George O.
Thin Film Module, Inc.
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