Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Electrical signal parameter measurement system
Reexamination Certificate
1998-09-08
2001-05-15
Shah, Kamini (Department: 2857)
Data processing: measuring, calibrating, or testing
Measurement system in a specific environment
Electrical signal parameter measurement system
C702S079000, C324S076590, C324S076820
Reexamination Certificate
active
06233528
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a signal-testing method, and to a signal-testing device also.
BACKGROUND OF THE INVENTION
The application of the phase locked loop is quite broad. Upon FM (frequency modulation) demodulation, the phase locked loop can be used to lock the phase of the signal for improving the sound effect. It is notorious the performance of the phase locked loop depends on how the signal phase is locked about which the present invention contemplates to ascertain.
FIG. 1
shows a basic circuit for a phase locked loop (PLL)
1
. On the one hand, the smaller the alignment difference between the input signal x and the output signal y is, the better the PLL performance will be. On the other hand, the smaller the jitter of the output signal y is or the stabler the output signal y is, the better the PLL performance will be.
As shown in
FIGS. 2A & 2B
, in the prior art, for obtaining the phase difference, a tester
2
set on a trigger mode with a trigger voltage adjusted on a specific level (normally one half of the high voltage, i.e. VDD/2) normally directly connects thereto input signal x and output signal y for obtaining time differences d
1
, d
2
, d
3
. . . between times when pulses of input signal x and output signal y respectively reach said specific level, and then averages the absolute values of time differences d
1
, d
2
, d
3
. . . to obtain the phase difference between input and output signals x, y.
It can be seen that input signal x and output signal y are connected to tester
2
through different paths. Ideally, two identical probes for tester
2
have the same equivalent impedance, and the contact impedances of the test clippers and the signal wires are also the same by which a good test result will be obtained, which, nevertheless, is impractical or impossible in the real world. For a signal in the megahertz or gigahertz frequency range, the included error in the tested result according to the prior art is unacceptable or is difficult to calculate.
As shown in
FIG. 3
, it has been the trend to use the PLL in a very large scale integration circuit (VLSI)
3
. Since paths a, b of input signal x and output signal y in the chip are different and thus incurred equivalent impedances thereof will be different, the tested error will be significant if the conventional testing method is applied.
As shown in
FIGS. 4A & 4B
, for measuring the jitter, tester
2
with a trigger voltage set at one half of the high voltage finds that pulses of output signal y begin to rise at times t
1
, t
2
, t
3
. . . After the time differences thereof d
1
, d
2
, d
3
. . . are calculated, we can average them to obtain the averaged cycle Tc. The maximum of the differential values d
1
-Tc, d
2
-Tc, d
3
-Tc . . . between respectively averaged cycle Tc and time differences d
1
, d
2
, d
3
. . . is the maximum jitter. On the contrary, the minimum of the differential values will be the minimum jitter.
It is therefore tried by the applicant to deal with the above situation encountered by the prior art and/or facilitate the test for the PLL.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a signal-testing method and device for facilitating the test of the phase difference and the jitter of a signal.
It is further an object of the present invention to provide a signal-testing method and device for reducing the error in measuring the phase difference.
It is still an object of the present invention to provide a signal-testing method and device for optionally measuring the phase difference and the jitter of a signal.
It is additional an object of the present invention to provide a signal-testing method and device for providing a multi-cycle jitter basis for a designer for more appropriately laying out the circuit.
It is yet an object of the present invention to provide a signal-testing method and device for minimizing the test pin number for an integrated circuit (IC).
According to a first aspect of the present invention, a signal-testing device adapted to be electrically connected to a tester for testing a first signal having a first state and a second state and a second signal having a third state and a fourth state includes a selected signal generator receiving the first signal and the second signal for generating a selected signal having a state which is changed when the first signal is in the first state and the second signal is in the third state, and a signal selector electrically connected to the selected signal generator for selectively outputting one of the first and second signals in response to the selected signal state.
Certainly, the first and the third states can be the same, and the second and the fourth states can also be the same.
Preferably the selected signal generator includes a first logic gate for outputting a clock signal having a state which is changed when the first signal is in the first state and the second signal is in the third state, and a flip-flop electrically connected to the first logic gate for outputting the selected signal where the selected signal state is changed in response to the clock signal state.
Certainly, the first logic gate can be a NOR gate. The clock signal state can be one selected from a group consisting of a low voltage state, a high voltage state, a state changing from the low voltage state into the high voltage state, and a state changing from the high voltage state into the low voltage state.
Preferably the flip-flop changes said selected signal state when the clock signal is in the state changing from the low voltage state into the high voltage state.
Certainly, the flip-flop can be a D-type flip-flop. The said selected signal state can be one of a low voltage state and a high voltage state. The signal selector can respectively select the first and the second signals when the selected signal is respectively in the low voltage and the high voltage states. The signal selector can be a multiplexer.
The selected signal generator can further include a second logic gate electrically connected to the flip-flop and having a test mode control end having an input voltage, in which the selected signal outputted from the flip-flop is kept in a first state to enable the signal selector to selectively output the second signal for testing a jitter of the output signal when the input voltage is in a first state, and the selected signal outputted from the flip-flop changes in response to the first and the second signals to enable the signal selector to respectively selectively output the first and the second signals for obtaining a phase difference between the first and the second signals when the input voltage is in a second state.
The second logic gate can be an AND gate. The first and the second states of the input voltage can be respectively in a low voltage and a high voltage. The present signal-testing device can further include the tester.
In accordance with the present invention, a signal-testing method includes the following steps of a) generating an output signal having a plurality of pulses in response to a first signal and a second signal, b) obtaining a plurality of time differences each of which represents a time difference between a time when a first one of the pulses reaches a specific voltage and a time when a second one of the pulses most adjacent to the first one pulse reaches the specific voltage, c) obtaining a plurality of absolute values of differences each of which represents a difference between most adjacent two of the plurality of time differences, and d) obtaining a phase difference by dividing by 2 an average value of the absolute values.
Certainly, the first signal and the second signal can be square waves and respectively have a plurality of pulses.
Preferably the selected signal includes a first portion and a second portion during which the first signal pulses and the second signal pulses respectively begin to rise until the first signal pulses and the second signal pulses respectively end to fall.
Certainly, the time differences have a number of 1,000.
Lai Jiin
Lin Hsin-Chieh
Lin Jyh-fong
Madson & Metcalf
Pretlow Demetrius
Shah Kamini
VIA Technologies Inc.
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