Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Having phase shift
Patent
1986-10-09
1987-12-08
Heyman, John S.
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Having phase shift
377 47, 328 63, 331 1A, H03L 718, H04L 702
Patent
active
047122234
ABSTRACT:
A digital phase locked loop to function as a stable reference clock given a gapped, or pulse stuffed, input clock signal which may have a frequency offset relative to the nominal specified frequency and a phase jitter relative to the average frequency of the input signal, the digital phase locked loop comprising an input synchronizer for synchronizing the input clock signal to a stable high frequency reference clock. The output of the input synchronizer increments a write counter and resets a phase counter to zero at the begininning of each cycle of the input clock signal. The outputs of the write counter and the phase counter are sampled by a sampling circuit which interprets the sampled data in two's complement form. A digital filter receives the output of the sampling circuit and performs a low pass filter function on the sampled data and calculates a linearized approximation of the frequency to be generated by the offset (non-symmetric) digitally controlled oscillator (ODCO) which receives the output of the digital filter. The ODCO uses its input to determine the frequency of discrete phase adjustments placed in its output signal. The output of the ODCO is divided by a read counter. Each time the read counter enters a predetermined state, the sampling circuit is caused to sample the input clock signal and the process is repeated again and again.
REFERENCES:
patent: 4577163 (1986-03-01), Culp
patent: 4627080 (1986-12-01), Debus, Jr.
Hamann H. Fredrick
Heyman John S.
Lutz Bruce C.
Rockwell International Corporation
Sewell V. L.
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