Method and system for storing and processing multiple memory add

Details Method and system for storing and processing multiple memory add Method and system for storing and processing multiple memory add

Filed on

1997-06-13

Date issued

1998-10-20

Examiner

Nelms, David C.

Patent Class

Static information storage and retrieval

SubClass

Addressing

SubSubClass

Plural blocks or banks

Other Related Categories

36523008, 36518905, G11C 800, G11C 700

Type

Patent

Status

active

Patent number

058257110

Description

ABSTRACT:
A packetized dynamic random access memory ("DRAM") receives command packets each of which contain a plurality of command words. One of the command words in each command packet includes a column address. Each of the command words, including the column address, is stored in one of a plurality of storage units so that a plurality of column addresses may be simultaneously stored in the storage units. The column addresses are individually coupled from respective storage units to a common column address bus which includes an address latch. The column address bus drives a column address processing circuit, such as a column address decoder. Also included is an adder that allows the DRAM to operate in a burst mode. In response to receiving an increment signal, the adder increments the column address at the output of the column address bus and applies the incremented address to the input of the column address bus.

REFERENCES:
patent: 5732041 (1998-03-01), Joffe
patent: 5737563 (1998-04-01), Shigeeda
Descriptive literature entitled, "400 MHz SLDRAM, 4M.times.16 SLDRAM Pipelined, Eight Bank, 2.5 V Operation," pp. 1-22.
"Draft Standard for a High-Speed Memory Interface (SyncLink)," Microprocessor and Microcomputer Standards Subcommittee of the IEEE Computer Society, Copyright 1996 by the Institute of Electrical and Electronics Engineers, Inc., New York, NY, pp. 1-56.

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