Method of reducing CMP dishing effect

Details Method of reducing CMP dishing effect Method of reducing CMP dishing effect

1999-07-15

2001-04-24

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S427000, C438S435000, C438S443000, C438S692000, C438S700000, C438S701000, C438S702000, C438S792000, C438S793000, C438S794000

Reexamination Certificate

active

06221734

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88108519, filed May 25, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a planarizing method in a semiconductor process. More particularly, the present invention relates to a method of reducing a dishing effect resulting from chemical mechanical polishing (CMP).
2. Description of Related Art
Among the various different semiconductor integrated circuit (IC) processes, surface planarization is one important technique of high-density photolithography treatment, because a planarized surface without height fluctuations can prevent light scattering and help a precise pattern transfer. When the semiconductor process is carried out at the deep sub micron level, CMP is currently the only technique that can provide global planarization for a very large scale integration (VLSI) or ultra large scale integration (ULSI), while also providing a desired planarization in the multilevel interconnect process.
However, there are still problems associated with CMP for a region with a large surface area in the deposition layer.
FIG. 1
is a cross-sectional diagram illustrating a CMP dishing effect, which occurs on the substrate surface in the prior art. From the diagram, it is seen that a substrate
10
, which is formed with recesses at different surface area (
11
and
12
), is provided. Consequently, a deposition layer
13
is formed on the substrate
10
to fill the recesses II and
12
with an uneven surface profile. After the surface of the deposition layer
13
is planarized by CMP, a region
14
with over the recess
10
of a large surface area has a lower surface level than the surrounding regions of the deposition layer
13
. This is known as a dishing effect.
The occurrence of a CMP dishing effect is mainly due to the fact that a polishing table has a flexible polishing pad. When CMP is performed on the substrate surface with height fluctuations, the polishing pad is located above the substrate surface. Therefore, the polishing pad may deform along the substrate profile when the polishing table applies a downward stress on the polishing pad. The polishing pad may bend more readily downwards to the region with a larger surface area than the surrounding regions, so that this region is polished prior to other regions, causing the dishing effect.
One approach for improving the dishing effect using dummy patterns has been developed. This involves forming several projecting supports in the recess of large surface area to sussequently form a deposition layer having a more even surface profile. As a result, the surface of the deposition layer becomes more planar after being polished without resulting in a dishing effect. The other approach for improving the dishing effect involves filling and planarizing the recess using surfactants with better mobility and flexibility. At the onset of polishing, the surface of the recess is protected. During the polishing step where the height difference of the substrate surface is reduced, the excessive surfactants slowly drip off to yield a uniform substrate surface. However, the two approaches mentioned above either require numerous steps or incur a high cost.
SUMMARY OF THE INVENTION
The invention provides a method of reducing a CMP dishing effect, in which a substrate is provided with a plurality of trenches formed thereon. A first insulating layer, such as a silicon oxide layer, is formed on the substrate to fill those trenches. A chemical reaction, for example, a nitridation reaction is performed on the surface of the first insulating layer to form a second insulating layer, which is harder than the first insulating layer. CMP is then performed.
As embodied and broadly described herein, the stronger second insulating layer is formed to protect the first insulating layer in the recess, so that no dishing effect results from performing CMP on the first insulating layer in the recess.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 4762728 (1988-08-01), Keyser et al.
patent: 5362669 (1994-11-01), Boyd et al.
patent: 5891809 (1999-04-01), Chau et al.
patent: 6017803 (2000-01-01), Wong

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