Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1999-09-15
2001-06-26
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S221000
Reexamination Certificate
active
06251750
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for manufacturing a semiconductor device. More particularly, the present invention relates to a method for manufacturing a shallow trench isolation.
2. Description of Related Art
An isolation region is formed in an integrated circuit for the purpose of separating neighboring device regions of a substrate and preventing the carriers from penetrating through the substrate to neighboring devices. Conventionally, the local oxidation of silicon (LOCOS) technique is widely utilized in semiconductor industry to provide isolation regions among the various devices in the substrate. Since the LOCOS technique has been used for quite a period of time, it is one of the most reliable and low-cost methods for fabricating device isolation region. However, the bird's beak structure of the field oxide formed by LOCOS technique limits the size of the integrated circuit. Hence, a shallow trench isolation (STI) technique has been developed and is currently applied in the integrated circuit process, especially in the sub-half micron integrated circuit process.
In the current process for manufacturing a STI, a silicon nitride layer is used as a mask layer and a trench is formed in the substrate by anisotropically etching. And then, an oxide material is deposited in the trench and fills the trench to form a STI. Next, a chemical-mechanical polishing step is used to planarize the oxide layer and to form an STI region. Therefore, the problem induced by the bird's beak can be overcome. However, the typical trench is a tapered trench; that is, the bottom of the trench is smaller than the opening of the trench. As line width becomes smaller and integration becomes higher, the width of the STI used to isolate the neighboring active regions is decreased. Hence, a bridging effect occurs between the neighboring active regions isolated by the STI. The bridging effect is especially obvious in processes below 0.18 microns.
SUMMARY OF THE INVENTION
The invention provides a method of manufacturing a shallow trench isolation in a substrate. The substrate has a pad oxide layer and a mask layer formed thereon in sequence and a trench penetrating through the mask layer and the pad oxide layer and into the substrate. A thermal oxidation process is performed to form a liner oxide layer on a portion of the substrate exposed by the trench. A spacer is formed on the sidewall of the mask layer, the pad oxide layer and the trench. An oxidation process is performed to oxidize a portion of the substrate under a portion of the liner oxide layer located on the bottom of the trench. An insulating layer is formed over the substrate and filling the trench. A planarization process is performed to remove a portion of the insulating layer until the mask layer is exposed. The mask layer and the pad oxide layer are removed.
As embodied and broadly described herein, during the oxidation process, the oxygen penetrates through the portion of the liner oxide layer exposed by the spacer on the bottom of the trench to oxidize the portion of the substrate under the exposed portion of the liner oxide layer. Therefore, a nubbly rough insulating layer is formed at the bottom of the trench. Because the undesirable current between the neighboring devices flows along the margin of the trench and the oxide layer in the substrate, the current channel distance between the neighboring devices is larger than the conventional current channel. Hence, the bridging effect does not occur between the neighboring devices.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5918131 (1999-06-01), Hsu et al.
patent: 5950090 (1999-09-01), Chen et al.
patent: 6093600 (2000-07-01), Chen et al.
patent: 6107159 (2000-08-01), Chuang
patent: 6121110 (2000-09-01), Hong et al.
Nelms David
Nhu David
United Microelectronics Corp.
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