Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
1999-02-02
2001-01-30
Williams, Alexander O. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S690000, C257S616000, C257S784000, C257S211000, C257S208000, C257S207000, C257S786000
Reexamination Certificate
active
06181005
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and, more specifically, to an improvement of a semiconductor package structure having reinforced power source.
2. Description of the Background Art
Recently, higher speed of operation has been required of semiconductor devices such as a DRAM (Dynamic Random Access Memory). As the speed of operation of the semiconductor device increases, generation of noise has come to be a serious problem. In order to prevent generation of noise, generally, power supply is reinforced by increasing number of bonding pads for the power supply provided in the semiconductor device.
FIG. 11
shows pin arrangement of a 256 megabit DRAM 100 standardized by JEDEC (Joint Electron Device Council). There are five power sources for supplying power supply potential (VDD) on the left column, and five power sources for supplying ground potential (VSS) on the right column.
At present, TSOP (Thin Small Outline Package) is dominant as the semiconductor package used for DRAMs and the like. The structure of the TSOP will be briefly described with reference to
FIGS. 12 and 13
.
FIG. 12
is a plan view showing the structure of the TSOP. For convenience, sealing resin is not shown.
FIG. 13
is a cross section taken along the line
13
—
13
′ of FIG.
12
.
As shown in these figures, the structure of the TSOP includes a silicon substrate
101
, and a semiconductor integrated circuit
105
formed on a main surface of silicon substrate
101
and covered by a passivation film
106
. Further, there is a plurality of bonding pads
102
formed for connection with the semiconductor integrated circuit
105
.
Bonding pads
102
are arranged along longitudinal sides of semiconductor integrated circuit
105
. A lead frame
103
for providing connection with external terminals by means of wirings
104
are connected to bonding pads
102
. Silicon substrate
101
, semiconductor integrated circuit
105
, passivation film
106
, bonding pads
102
, wirings
104
and part of the lead frame
103
are sealed by a resin
107
.
A structure of a LOC type TSOP, which is an improvement of the TSOP above will be described with reference to
FIGS. 14 and 15
.
FIG. 14
is a plan view showing the structure of the LOC type TSOP. For convenience, sealing resin is not shown.
FIG. 15
is a cross section taken along the line
15
—
15
′ of FIG.
14
.
As shown in these figures, the structure of the LOC type TSOP includes a semiconductor integrated circuit
115
formed on a silicon substrate
111
, and bonding pads
112
arranged in one line at the center of silicon substrate
111
for connection with the semiconductor integrated circuit
115
. Semiconductor integrated circuit
115
is covered by a passivation film
116
. A lead frame
113
is arranged to extend above semiconductor integrated circuit
115
with a film coat
117
on passivation film
116
interposed.
Lead frame
113
is connected to bonding pads
112
by means of wirings
114
. Silicon substrate
111
, semiconductor integrated circuit
115
, passivation film
116
, film coat
117
, bonding pads
112
, wirings
114
and part of the lead frame
113
are sealed by resin
118
.
When we compare the structure of the conventional type TSOP shown in FIG.
13
and the LOC type TSOP shown in
FIG. 15
, in the LOC type TSOP, a distance x
2
between a side surface of sealing resin
118
and a side surface of silicon substrate
111
can be made shorter than a distance x
1
in the conventional TSOP, as the lead frame
113
extends above semiconductor integrated circuit
115
. Since the outer dimension of the sealing resin has been standardized, a semiconductor circuit having higher degree of integration can be used, and area of the semiconductor integrated circuit can be enlarged within the same shape.
A structure of a path bar type TSOP which is an improvement of LOC type TSOP will be described with reference to
FIGS. 16 and 17
.
FIG. 16
is a plan view showing the structure of the path bar type TSOP. For convenience, sealing resin is not shown.
FIG. 17
is a cross section taken along the line
17
—
17
of FIG.
16
.
As shown in these figures, the structure of the path bar type TSOP is, basically, similar to the structure of the conventional LOC type TSOP. A semiconductor integrated circuit
128
is formed on a silicon substrate
121
, and bonding pads
122
for connection with the semiconductor integrated circuit
128
are arranged in one line at the center of silicon substrate
121
.
Semiconductor integrated circuit
128
is covered by a passivation film
127
. Lead frame
123
is arranged extending above semiconductor integrated circuit
128
with film coat
126
on passivation film
127
interposed. Further, lead frame
123
is connected to bonding pads
122
by wirings
129
. Silicon substrate
121
, semiconductor integrated circuit
128
, passivation film
127
, film coat
126
, bonding pads
122
, wirings
129
and part of the lead frame
123
are sealed by resin.
In the path bar type TSOP structure, in order to reinforce power sources to prevent generation of noise, number of bonding pads for power sources provided in the semiconductor device has been increased. As shown in the plan view of
FIG. 16
, an auxiliary lead frame
125
is arranged along bonding pads
122
, which is connected to lead frame
123
for the power supply line. By providing auxiliary lead frame
125
connected to the power supply line, it becomes possible to provide power source pads at arbitrary positions, so that power source of the semiconductor device can be reinforced.
Meanwhile, a BGA (Ball Grid Array) has been studied as a new package for a semiconductor device such as a DRAM. The structure of the BGA will be briefly described with reference to
FIGS. 18 and 19
.
FIG. 18
is a perspective view showing schematic structure of the BGA, and
FIG. 19
is a perspective view of the rear surface of the BGA.
Referring to these figures, on a substrate
141
provided with interconnections printed thereon, a chip
143
having a semiconductor integrated circuit formed therein is mounted, and chip
143
is connected to printed interconnections of substrate
141
by means of wirings
144
. Printed interconnections, wirings
144
and chip
143
are sealed by an epoxy resin
142
.
On the rear surface, a plurality of bump electrodes
145
formed of spherical solder, for example, are arranged in an array, and these function similar to the lead frame of the conventional TSOP structure described above. Substrate
141
has multilayered interconnection structure, and prescribed bump electrodes
145
are connected to the printed circuit board.
In the path bar structure shown in
FIGS. 16 and 17
, it is necessary to arrange bonding pads
122
at the central portion of silicon substrate
121
. However, when the number of bonding pads
121
is increased to reinforce the power source, there is a limit in the increase of the number of bonding pads
121
arranged in one line, as the size of the semiconductor device is standardized. It may be possible to arrange bonding pads
122
in two lines at the center of silicon substrate
121
. However, in that case, there would be long and complicated extensions of power supply lines provided by wirings. As a result, there would be voltage drop over the power supply lines, which makes it difficult to reinforce the power source.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device which can reinforce power source by shortening the distance of power supply line extension provided by wirings.
According to one aspect of the present invention, the semiconductor device includes a semiconductor integrated circuit provided on a main surface of a semiconductor substrate, a plurality of bonding pads provided for connection with the semiconductor integrated circuit, arranged on opposing longitudinal sides of the semiconductor integrated circuit on the main surface of the semiconductor substrate, an interconnection layer connected by means o
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Williams Alexander O.
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