Static information storage and retrieval – Floating gate – Multiple values
Patent
1997-08-11
1998-10-20
Le, Vu A.
Static information storage and retrieval
Floating gate
Multiple values
365 94, 365104, 365105, G11C 1134
Patent
active
058256865
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
Conventional memory cells can each store 1 bit of information. The two states of the cell may be, for example, a high or low threshold voltage of the transistor in a 1-transistor memory cell. During the read-out operation, the bit lines in many known arrangements are initially precharged to a defined voltage. When the cell is driven via the word line, the charge of the bit line connected to the cell is changed to a greater or lesser extent depending on the state of the cell. In this way, the information of the cell can be read out via a high or low level of the bit line. In order to achieve high interference immunity, the two levels must have the maximum possible voltage difference, for example positive supply voltage and 0 volts.
In order to increase the information density, multi-value memory cells have also occasionally been used, in particular in read-only memories. Multi-value memory cells are memory cells which each have a storage capacity of more than 1 bit.
The international patent application with the publication number WO 82/02977 has disclosed a mask-programmable read-only memory (ROM) in whose memory cells it is possible to store more than only two logic states. In order to obtain cells each having the same, minimum size, the logic states are in this case programmed into the cells by setting the threshold voltage of the transistor situated in the respective cell separately in each case.
This necessitates the reliable differentiation between a plurality, for example four, of different voltage or current values. This means a higher outlay on circuitry, for example for stabilized reference voltages, and, above all, a reduced interference immunity. This can also lead to reduced efficiency. This, presumably, is why multi-value memory cells have not attained any practical significance to date. In modern memories with a reduced supply voltage, for example with 3.3 V, the disadvantages cited are even less acceptable.
The document GB-A-2 157 489 discloses a multi-value read-only memory cell which is of symmetrical construction for storing a first or second state and of asymmetrical construction for storing a third or fourth state.
SUMMARY OF THE INVENTION
The invention is based on the object, then, of specifying a multi-value memory cell in which the minimum possible outlay on circuitry is required and in which the signal-to-noise ratio is significantly improved in comparison with known multi-value memory cells.
In general terms the present invention is a multi-value read-only memory cell has symmetrical construction for storing one of a first state and a second state and having asymmetrical construction for storing at least a third state. A MOS field-effect transistor has a source/drain region situated in a semiconductor body and has a drain/source region situated in the semiconductor body. In order to store the first state, a first cell connection is connected directly to the source/drain region of the MOS field-effect transistor and a second cell connection is connected directly to the drain/source region of the MOS field-effect transistor. In order to store the second state, the first cell connection is connected via a first component to the source/drain region of the MOS field-effect transistor, and the second cell connection is connected via a second component to the drain/source region of the MOS field-effect transistor. In order to store the third state, the first cell connection is connected via the first component to the source/drain region of the MOS field-effect transistor, and the second cell connection is connected directly to the drain/source region of the MOS field-effect transistor. In order to store a fourth state, the first cell connection is connected directly to the source/drain region of the MOS field-effect transistor and the second cell connection is connected via the second component to the drain/source region of the MOS field-effect transistor. A third cell connection is connected to a gate electrode of the MOS field-effect transistor, drain/sour
REFERENCES:
patent: 5296726 (1994-03-01), MacElwee
patent: 5402374 (1995-03-01), Tsuruta et al.
IBM Technical Disclosure Bulletin, vol. 28, No. 7, Dec. (1985), New York, "Read only memory", pp. 3048-3049.
Bollu Michael
Schmitt-Landsiedel Doris
Thewes Roland
VON Basse Paul-Werner
Le Vu A.
Siemens Aktiengesellschaft
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