Stress-follower circuit configuration

Details Stress-follower circuit configuration Stress-follower circuit configuration

2001-01-02

2001-09-04

Leja, Ronald W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C326S083000

Reexamination Certificate

active

06285537

ABSTRACT:

BACKGROUND
1. Field
The invention is related to transistors, and more particularly, to a stress-follower circuit configuration to protect such transistors.
2. Background Information
As is well-known, transistors may suffer from Electrical Over Stress (EOS), which in this context refers to the application of voltages above the specified safe range of an electrical device, and may result in device degradation. This may occur, for example, when the transistor is employed in the manner using a significantly higher operating voltage than the native process transistors are able to tolerate. Native process transistors are the basic building blocks of a semiconductor process. For example, a 0.25 micron semiconductor fabrication process may have native transistors with specified operating voltages of 1.8 to 2.5 volts. However, if a technique or approach were devised in which these transistors could tolerate these higher operating voltages, this would allow devices and/or systems operating at higher voltages to be created using this technology. In today's environment typically legacy devices, components, or systems, such as those employing or combining with Peripheral Component Interconnect (PCI), Accelerated Graphics Port (AGP), or Dynamic Random Access Memory (DRAM), for example, employ higher voltages than state-of-the art transistors fabricated using native processes.
SUMMARY
Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a stress-follower circuit configuration. The stress-follower circuit of the configuration is coupled to a pad of the integrated circuit. The stress-follower circuit configuration is coupled so as to reduce the voltage stress on the gate of a transistor in a transistor stack so that in operation the transistor in the stack tolerates an operating voltage approximately 1.5 volts above its nominal voltage. The transistor stack is also coupled to the pad.


REFERENCES:
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patent: 5576635 (1996-11-01), Partovi et al.
patent: 5731714 (1998-03-01), Monk et al.
patent: 5804998 (1998-09-01), Cahill et al.
patent: 5852540 (1998-12-01), Haider
patent: 6054875 (2000-04-01), Wayner

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