Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
1999-04-23
2001-04-24
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S155000
Reexamination Certificate
active
06222478
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates in general to signal processing, and more particularly to a pipeline analog-to-digital conversion system using a modified coding scheme and method of operation.
BACKGROUND OF THE INVENTION
Many electronic systems manipulate both digital and analog signals. To perform their intended function, these systems may convert analog signals into digital signals. For example, digital signal processing technology facilitates the economical and accurate transmission of either analog or digital signals to a remote receiver. In a particular application, signals in digital communications systems are transmitted as a sequence of binary pulses with the advantage that corruption of the amplitudes of these pulses by noise is, to a large extent, of no consequence. In contrast, digital video disk systems transmit and receive analog signals. In order to operate, however, these systems require circuitry to interface signals from the analog domain to signals in the digital domain so that they may perform further digital signal processing. Specifically, these systems require analog-to-digital conversion systems to interface the analog and digital domains. Advances in digital video disk systems and other related technologies indicate a need for increased conversion rates in analog-to-digital conversion systems.
Traditional analog-to-digital conversion systems use flash architectures or pipeline architectures to obtain 8-bit resolution at approximately the same conversion rate as each other. For more than 8-bit resolution, however, flash architectures are no longer feasible alternatives because they require large die areas and power dissipation. Pipeline conversion architectures attempt to reduce die areas and power requirements while increasing the conversion rate for resolutions greater than 8-bit. A March, 1992 article in the IEEE Journal of Solid-State Circuits, authored by Lewis, et al. and entitled “A 10-b 20-Msample/s Analog-to-Digital Converter,” describes a particular prior art pipeline conversion system. However, these prior art systems still do not realize the optimum conversion rates attainable for a pipeline conversion system with a particular range of die areas and power dissipation.
SUMMARY OF THE INVENTION
In accordance with the teachings of the present invention, a pipeline analog-to-digital conversion system is provided which substantially increases the efficiency of prior pipeline analog-to-digital conversion systems.
In accordance with one embodiment of the present invention, an analog-to-digital conversion system includes a plurality of cascaded subconverter stages wherein at least one of the plurality of subconverter stages includes an analog-to-digital converter that receives from a previous stage a first input analog signal and a corresponding first intermediate digital signal. The analog-to-digital converter generates a second intermediate digital signal in response to the first input analog signal and the first intermediate digital signal. A digital-to-analog converter coupled to the analog-to-digital converter converts the second intermediate digital signal into an intermediate analog signal. An arithmetic unit coupled to the digital-to-analog converter receives the intermediate analog signal and a second input analog signal and generates an output analog signal representative of the difference between the second input analog signal and the intermediate analog signal.
Another embodiment of the present invention is a method for converting an analog signal into a digital signal, wherein at least one of a plurality of cascaded subconverter stages receives from a previous stage a first input analog signal and a corresponding first intermediate digital signal, and establishes a plurality of voltage thresholds in response to the first intermediate digital signal. The method further includes generating a second intermediate digital signal in response to the first input analog signal and the voltage thresholds. The method concludes by converting the second intermediate digital signal into an intermediate analog signal and generating an output analog signal representative of the difference between a second input analog signal and the intermediate analog signal.
Technical advantages of the present invention include an analog-to-digital conversion system with a decreased throughput delay time for each individual subconverter stage and a decreased latency delay time for the entire system, resulting in an increased analog-to-digital conversion rate. The throughput delay time for each stage of a prior analog-to-digital conversion system includes the time required by the analog-to-digital converter to create an intermediate digital signal as a function of an input analog signal, and the time required by the digital-to-analog converter to create an intermediate analog signal as a function of the intermediate digital signal.
Unlike prior systems, each subconverter stage of the present invention generates an intermediate digital signal as a function of the intermediate digital signal and input analog signal of the previous stage. This allows the current subconverter stage to generate an intermediate analog signal while the previous stage generates an input analog signal. As a result, the delay times associated with generating an intermediate digital signal and an intermediate analog signal are substantially eliminated from the throughput delay time of each individual stage.
The throughput delay time for the present invention therefore comprises only the time required by the arithmetic unit to perform the arithmetic operation. As a result, the throughput delay time for each individual stage decreases in comparison to prior pipeline conversion systems. Since the latency delay time of the conversion system comprises the sum of all of the individual throughput delay times for each stage, the latency also decreases in comparison to prior pipeline conversion systems. Since the analog-to-digital conversion rate of the system bears an inverse relationship to the throughput delay time and the latency delay time, the analog-to-digital conversion rate for the system increases in comparison to prior systems.
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Stephen H. Lewis, et al., “A 10-b 20-Msample/s Analog-to-Digital Converter,” IEEE Journal of Solid-State Circuits, vol. 27, No. 3, Mar., 1992, 8 pages.
Bret C. Rothenberg, et al., “A 20-Msample/s Switched-Capacitor Finite-Impulse-Response Filter Using a Transposed Structure,” IEEE Journal of Solid-State Circuits, vol. 30, No. 12, Dec., 1995, 7 pages.
Brady III Wade James
Holmbo Dwight N.
Jean-Pierre Peguy
Jeanglaude Jean Bruner
Telecky , Jr. Frederick J.
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