Chemistry: electrical and wave energy – Apparatus – Electrolytic
Reexamination Certificate
1998-09-17
2001-09-25
Valentine, Donald R. (Department: 1741)
Chemistry: electrical and wave energy
Apparatus
Electrolytic
C204S22400M, C204S22400M, C118S066000, C118S423000, C118S429000, C118S500000, C134S902000
Reexamination Certificate
active
06294059
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a substrate plating apparatus for plating a substrate, and more particularly to a substrate plating apparatus for forming a metal interconnection layer in an interconnection region composed of a fine groove and/or a fine hole defined in a substrate such as a semiconductor wafer or the like.
2. Description of the Related Art
For forming an interconnection circuit on a semiconductor substrate, it has been customary to deposit a conductive film on a surface of the semiconductor substrate by sputtering or the like, and remove unwanted areas of the conductive film by chemical dry etching using a pattern mask such as a resist or the like.
The material of the interconnection circuit has generally been aluminum (Al) or aluminum alloy. Highly integrated semiconductor circuits have thinner interconnections, which result in increased current densities that are responsible for increased thermal stresses and temperature rises. As aluminum films become thinner due to stress migration or electromigration, these problems manifest themselves to the point where interconnections tend to be broken down or short-circuited.
Thus, there is a greater demand for using conductive materials such as copper (Cu) for forming these interconnections, in order to realize lower conductivity and to avoid electromigrations due to currents flowing therethrough. However, since it is difficult to remove copper or its alloy by dry etching, the conventional process of depositing a copper film and then patterning the copper film by dry etching cannot be relied upon for producing interconnections on substrates. One solution is to form a desired pattern of interconnection grooves in a substrate surface, and then fill the interconnection grooves with copper or its alloy. This process does not require any etching process to remove unwanted copper or its alloy. Instead, surface irregularities or steps are removed from the substrate surface by a polishing process. The process is also advantageous in that interconnection holes for interconnecting vertical circuit layers can also be formed simultaneously.
However, as the width of interconnections becomes thinner, those interconnection grooves or holes have a higher aspect ratio, i.e., a higher ratio of their depth to their diameter or width, and cannot uniformly be filled with copper or its alloy by performing a sputtering operation.
Chemical vapor deposition (CVD) is widely used for forming films of various materials. Nevertheless, the application of CVD for the formation of films of copper or its alloy is not promising because it is difficult to prepare a suitable gaseous material as a source of copper or its alloy. If an organic material is used, carbon (C) tends to be introduced from the organic material into a deposited film, resulting in greater electrical resistivity.
There has been proposed a plating process for depositing a copper film on a substrate. According to the proposed plating process, a substrate is immersed in a plating solution to plate the substrate with copper i.e. an electroless plating or electroplating procedure, and then unwanted areas of the plated copper layer is removed by chemical mechanical polishing (CMP). The plating process makes it possible to fill interconnection grooves of high aspect ratios uniformly with a highly conductive copper metal. When the plating process is continuously carried out within a clean atmosphere in a semiconductor fabrication facility, however, chemicals or solutions used in a pretreatment process and the plating process are spread as a chemical mist or gas, which tends to be attached to clean substrates that have been processed in the semiconductor fabrication facility. This problem arises even if the pretreatment process and the plating process are performed in a sealed processing chamber. Specifically, since the sealed processing chamber has to be opened for loading and unloading substrates, the chemical mist or gas generated in the plating bath or pretreatment bath or chamber cannot be prevented from spreading into the semiconductor fabrication facility.
It has been desired to develop a single apparatus or chamber for forming a plated copper layer on a surface of a semiconductor wafer including interconnection regions, which is composed of fine grooves and fine holes, by performing an electroless plating or electroplating operation, and then removing unwanted copper layer portions by performing a chemical mechanical polishing operation, thereby leaving the plated copper layer only in the interconnection regions. However, such a single apparatus or chamber has not been put to practical use.
If a substrate plating apparatus and a chemical mechanical polishing apparatus are separate from each other, then a semiconductor wafer plated with a copper layer has to be dried and unloaded from the substrate plating apparatus, and then a dried semiconductor wafer is loaded into the chemical mechanical polishing apparatus for removing unwanted copper portions. Therefore, two separate drying apparatuses or chambers are necessary. In some applications, a protective plated layer is deposited on a plated copper interconnection layer for protecting its surface. However, since the substrate plating apparatus is separate from the chemical mechanical polishing apparatus, the surface of the protective plated layer tends to be oxidized during the wafer transfer from the substrate plating apparatus to the chemical mechanical polishing apparatus.
The substrate plating apparatus generally comprises a loading and unloading area for transferring cassettes, which store substrates, a plating area for plating substrates, and a cleaning and drying area for cleaning and drying plated substrates. If the substrate plating apparatus, i.e., a wet processing bath which is accommodated in a chamber, is placed in a clean room for semiconductor fabrication facilities, then it is necessary to prevent particles, mists and gasses generated from a plating solution or a cleaning solution from being applied to semiconductor wafers which have already been processed and dried. Stated otherwise, when processed semiconductor wafers are unloaded from the substrate plating apparatus and transferred to a next processing stage, the particles, mists and gasses from the plating solution or the cleaning solution should not be spread into the clean room, where other manufacturing processes are carried out.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a substrate plating apparatus which is free of the various conventional problems even when placed in a clean room accommodating semiconductor fabrication facilities. A second object of the present invention is to provide a substrate plating apparatus which is capable of performing, with a unitary arrangement, various processing operations including forming a plated layer on a surface of a substrate including interconnection regions composed of fine interconnection grooves and fine interconnection holes and a removing unwanted layer portions from the substrate, thereby leaving the plated layer in the interconnection regions as an interconnection layer on the substrate.
Another object of the present invention is to provide a substrate plating apparatus which is effective to prevent particles, mists and gasses of a plating solution and a cleaning solution from spreading into a clean room as plated semiconductor wafers are transferred in the clean room from the plating apparatus to further processing equipment. These particles, mist and gasses are also prevented from spreading into a cleaning and drying area of the substrate plating apparatus.
According to the present invention, there is provided a substrate plating apparatus for forming an interconnection layer on an interconnection region composed of a fine groove and/or a fine hole defined in a substrate, comprising: first plating unit for forming a layer on a surface of the substrate including the interconnection region; a, first chemical mechanica
Chono Atsushi
Hongo Akihisa
Inoue Hiroaki
Kimura Norio
Kuriyama Fumio
Ebara Corporation
Valentine Donald R.
Wenderoth , Lind & Ponack, L.L.P.
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