Method and device for correcting errors in memories

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371 39, G06F 1110

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047122161

ABSTRACT:
The bit configurations are arranged in M-bit code words, each word comprising a number D of data bits and an even number N of error correcting bits. The data bits are partitioned into N fields with an error correcting bit associated with each field to indicate the parity of the associated field. The assignment of data bits to the N fields in such that, when the N fields are used to generate an N-bit error syndrome, this syndrome will contain an odd number n1 of bits at a first value if there is a single bit in error, where N-n1=n2 is also odd, and an even number of bits different from N to indicate a two-bit error. The number of bits of the first value are then used to determine whether the codeword is in its true or inverted form.

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Evans, "Nelson Matrix Can Pin Down Two Errors Per Word", Electronics International, vol. 55, No. 11, 6/82, pp. 158-162.

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