Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Reexamination Certificate
1999-09-16
2001-01-23
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Insulating material
C257S730000, C257S737000, C257S778000, C257S787000
Reexamination Certificate
active
06177724
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a mold package structure (ball giid array package or land grid array package) obtained by sealing a semiconductor chip loaded on a frame of an organic material such as glass epoxy resin with resin by transfer molding.
2. Description of the Prior Art
In a semiconductor device having a mold package structure (BGA or LGA) employing a frame of an organic material such as glass epoxy resin, a semiconductor chip loaded on the frame is sealed with resin by transfer molding.
The frame is previously formed with pads connected with the semiconductor chip through inner bumps or by flip chip bonding, pads forming external connection electrodes and wiring patterns coupling the pads with each other.
FIGS. 11 and 12
show structures of semiconductor chips loaded on frames respectively.
FIG. 11
shows a flip chip bonding structure obtained by directing the active surface of a semiconductor chip
4
downward (face down bonding) to wiring patterns
6
provided on the surface of a frame
2
and electrically connecting pad electrodes (not shown) of the semiconductor chip
4
with the wiring patterns
6
through inner bumps
5
. The semiconductor chip
4
and the inner bumps
5
are sealed with a package
1
.
FIG. 12
shows a wire bonding structure obtained by directing the active surface of a semiconductor chip
4
upward (face up bonding) to wiring patterns
6
provided on the surface of a frame
2
and fixing the semiconductor chip
4
to the frame
2
with a die bonding material
8
while electrically connecting pad electrodes (not shown) of the semiconductor chip
4
with the wiring patterns
6
through metal thin wires
7
. The semiconductor chip
4
and the metal thin wires
7
are sealed with resin
1
. After the semiconductor chip
4
is sealed with resin, external connection electrodes are formed on the rear surface of the frame
2
in each of the flip chip bonding structure and the wire bonding structure. The external connection electrodes may be formed by wires of the frame
2
themselves, or balls consisting of solder or the like. After formation of the external connection electrodes, the frame
2
is divided into a fragment with a mold or a laser beam, thereby completing a semiconductor device sealed with resin.
In the conventional semiconductor device having the aforementioned mold package structure, the overall loaded surface of the chip
4
is sealed with resin by transfer molding in an area equivalent to that of the frame
2
.
If the ratio of the area occupied by the semiconductor chip
4
to the total area of the frame
2
is small, however, the package is considerably warped as shown in
FIG. 13
or
14
. Thus, the package is restricted in size with respect to the semiconductor chip
4
.
Particularly when the package is at least 15 mm square in size and has at least 250 external connection electrode pins, warpage of the package may exceed 0.1 mm depending on the chip size, to result in the following problems:
Warpage of the package directly correlates with the flatness of the external connection electrodes. If the package is remarkably warped, the external connection electrodes of the semiconductor device are not connected with wires of a printed board.
The resin employed for transfer molding remarkably hardens/shrinks as the thickness thereof increases. If the resin sealing the semiconductor device has a large thickness, therefore, the package is inevitably remarkably warped.
Also when the loaded surface of the semiconductor chip is not entirely sealed with resin in an area equivalent to that of the frame but only a chip area is sealed with resin, the flatness of the external connection electrodes is deteriorated due to warpage of the mold package.
This defect tends to occur when the employed frame is extremely thin (about 0.1 mm), conceivably because of winding or warpage of the frame partially exposed on the outside of the semiconductor chip area. In the structure of this mold package, the strength of the package itself is extremely reduced, to conceivably result in inconvenience when the package is mounted on a printed board or the like.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device comprising a package sealing a semiconductor chip loaded on the surface of a flat frame consisting of an organic material such as glass epoxy resin with resin by transfer molding and an external connection electrode provided on the rear surface of the frame, having a structure capable of preventing the package from warpage.
The semiconductor device according to the present invention has a package sealing a semiconductor chip loaded on the surface of a flat frame consisting of an organic material such as glass epoxy resin with resin by transfer molding and an external connection electrode provided on the rear surface of the frame. The package includes a first region where a chip area equivalent to or slightly larger than the semiconductor chip is sealed with resin and a second region sealed with resin on the outside of the first region in a thickness smaller than that of the first region.
According to the aforementioned structure, warpage of the package can be reduced as compared with the case of thickly sealing the overall frame with resin. This is because the amount of resin is reduced in the second region on the outside of the semiconductor chip area and hence warpage of the package resulting from hardening/shrinkage of the resin in this portion can be reduced. In the first region, the overall loaded surface of the semiconductor chip is sealed with resin, whereby the strength of the package is ensured by the strength of the resin.
In order to implement the present invention in a more preferred state, the following structure is employed:
Preferably, the semiconductor device has mold ribs radially extending from the four corners of the first region toward those of the package on an upper surface part of the second region. Preferably, the semiconductor device has a mold ring on the upper surface part of the package, to enclose the outer peripheral portion thereof.
When the mold ribs or the mold ring is provided on the upper surface part of the second region, warpage of the package can be reduced without thickly sealing the overall frame. Further, the mold ribs or the mold ring ensures the strength of the package.
Preferably, the semiconductor device has internal draw parts on the four corners of the first region. Preferably, the internal draw parts have at least two types of sectional shapes or sectional dimensions. Preferably, the semiconductor device has an external draw part on at least one of regions of the mold ribs located on the four corners of the package. Preferably, the sectional shapes or sectional dimensions of the internal draw parts are smaller than that of the external draw part. Preferably, the semiconductor device has at least one portion of rib draw part on the mold ribs. Preferably, the semiconductor device has at least one portion of ring draw part on the mold ring.
According to this structure, the resin draw parts can supply proper heat to flowing resin, while unnecessary portions can be readily broken along the draw parts when removed after hardening of the resin.
The sectional shapes or sectional dimensions of the internal draw parts are rendered smaller than that of the external draw part, thereby suppressing heat reception of the sealing resin before reaching the first region and enabling injection of completely melted resin having low viscosity into the first region.
Consequently, damage on the internal structural parts such as the semiconductor chip and gold wires can be reduced when injecting resin into the first region, which is the semiconductor chip area.
The internal draw parts have at least two types of sectional dimensions since part of resin passing through the internal draw part having the largest sectional dimension dominantly flows into the first region, so that the resin can be prevented fro
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Potter Roy
LandOfFree
Semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2523183