Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Reexamination Certificate
1998-03-30
2001-07-31
Bowers, Charles (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
C438S959000, C438S401000, C438S462000, C257S618000
Reexamination Certificate
active
06268641
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor wafer having an identification indication and a method of manufacturing a semiconductor wafer having an identification indication.
Conventionally, an individual identification indication such as numerals and bar codes is applied to each semiconductor wafer before forming a semiconductor circuit on the semiconductor wafer so as to identify each semiconductor wafer. The indication is provided by engraving the front surface or the rear surface of the semiconductor wafer, in general, by means of laser beam radiation. However, various treatment processes are applied to the semiconductor wafer thereafter in order to form a semiconductor circuit in each chip area. After the treatment processes, the identification indication disappears or becomes unclear so that the recognition of the identification indication becomes difficult.
FIGS. 14 and 15
show a conventional semiconductor wafer
104
with a chip pattern
102
and an identification indication
16
formed on the surface of the semiconductor wafer
104
. The identification indication
16
is formed by engraving the wafer
104
by laser beam radiation. A layer film (single layer or multi-layer) such as an insulating film
106
is formed on the semiconductor wafer surface having the identification indication
16
.
FIG. 14
is a diagram showing the surface of the semiconductor wafer
104
with engraving, that is, the identification indication
16
formed thereon by the laser beam radiation.
FIG. 15
is an enlarged cross-sectional view of a part of the engraved portion, that is, the identification indication
16
portion on the semiconductor wafer surface of FIG.
14
. As shown in the cross-sectional view of
FIG. 15
, the wafer
104
is engraved by the laser beam substantially vertically with respect to the surface with a clear outline so that the indication can be read accurately before forming the insulating film
106
. However, if the insulating film
106
is formed on the semiconductor wafer surface, it is difficult to accurately reflect the outline of the engraved portion on the semiconductor wafer surface to the surface of the insulating film
106
so that the outline reflected on the insulating film
106
surface becomes unclear with dull corners. Therefore, it is difficult to read the indication accurately after forming the thin film. That is, if the insulating film
106
is formed by the CVD technology, the outline of the groove portion is ruined so that the outline of the insulating film
106
becomes a smooth mountain-like shape as shown in the cross-sectional view of FIG.
15
. Also, the outline of the engraving formed on the substrate surface becomes unclear, and thus accurate reading becomes difficult.
FIG. 16
shows the state where the surface of the insulating film
106
is applied with the CMP treatment, and further, a metal film
108
of, for example, Al is formed thereon in the cross-sectional structure of FIG.
14
. In this case, since the surface of the insulating film
106
is flattened by the CMP treatment, the surface of the metal film formed on the insulating film
106
can be flat as well. Therefore, when the CMP treatment is applied, the outline of the identification indication
16
, that is, the engraved portion disappears on the metal film so that the identification indication
16
cannot be read out.
FIG. 17
shows the semiconductor wafer surface with a chip pattern
102
formed on the entirety thereof so as to minimize the loading effect of the RIE treatment and/or the CMP treatment. By forming the chip pattern on the entirety of the semiconductor wafer surface, the outline of the engraving of the identification indication
16
formed on the semiconductor wafer surface before forming the chip pattern becomes unclear as the semiconductor circuit formation treatment process proceeds on the wafer surface so that the accurate reading of the identification indication
16
becomes difficult.
FIG. 18
is a plan view of the semiconductor wafer surface with the engraving formed thereon.
FIG. 19
is an enlarged cross-sectional view of a part of the engraved portion. If the engraving is formed on the surface of the semiconductor wafer
104
by the laser beam radiation, actually not only the groove but also a bump (uplift)
202
is formed in the engraved portion as shown in FIG.
19
. Due to the bump
202
, the homogeneity of the flatness is deteriorated in the subsequent CMP treatment. That is, since an abrading pad (not illustrated) of an abrading device cannot or hardly makes contact with the rear part of the semiconductor wafer
104
at the time of contacting and abrading the bump
202
of the engraved portion due to the height of the bump
202
, an under polish is generated on the semiconductor wafer surface portion in the vicinity of the bump
202
. Furthermore, when attaching such a wafer with a bump on a stage in a stepper, the bump portion of the wafer rises so that the light beam cannot be focused well in the lithography.
FIG. 20
is a side view of the semiconductor wafer
104
where the identification indication
16
is formed by engraving the rear surface of the semiconductor wafer
104
by the laser beam radiation. The rear surface of the semiconductor is, however, applied with the wrapping treatment (backside grinding) preceding the packaging, and thus by the wrapping treatment, the wafer
104
(such as a silicon substrate) usually having about 725 um thickness becomes thinner to about 300 um thickness. By the wrapping treatment, the identification indication
16
by engraving is completely eliminated without remaining until the cutting and separating process of the wafer
104
into chips.
As heretofore mentioned, in the case the identification indication
16
is formed on the surface of the wafer, the outline of the engraving on the semiconductor wafer surface disappears or becomes unclear by the subsequent processes on the wafer surface for forming a semiconductor circuit so that it becomes difficult to read the identification indication
16
. On the other hand, in the case the identification indication
16
is formed on the rear side of the wafer, the identification indication
16
by engraving completely disappears by the wrapping treatment of the wafer rear surface preceding the packaging and thus it is impossible to read the identification indication
16
.
BRIEF SUMMARY OF THE INVENTION
In order to solve the above-mentioned problems, an object of the present invention is to provide a semiconductor wafer having an identification indication capable of maintaining the identification indication formed by engraving in a clearly recognizable state until the wafer is cut and separated into chips without having the identification indication for identifying the wafer disappear or become unclear even after the treatment process on the wafer surface for forming a semiconductor circuit, or even after the treatment process after the wrapping treatment process on the wafer rear surface, and a method of manufacturing a semiconductor wafer having an identification indication.
In order to achieve the above-mentioned object, in the present invention, the identification indication for identifying the semiconductor wafer is formed on a selected side surface portion of the semiconductor wafer to remain after performing the semiconductor wafer abrading treatment from the rear side for making the semiconductor wafer thinner.
The present invention is to provide a semiconductor wafer having a semiconductor wafer identification indication on a selected side surface portion of the semiconductor wafer to remain after performing the semiconductor wafer abrading treatment from the rear side for making the semiconductor wafer thinner.
The side surface of the semiconductor wafer may have a slant face portion elongating from the front surface, a slant face portion elongating from the rear surface, and a peripheral surface portion between the slant face portion elongating from the front surface and the slant face portion elongating from the rear sur
Okumura Katsuya
Yano Hiroyuki
Banner & Witcoff , Ltd.
Bowers Charles
Hawramak Scott J
Kabushiki Kaisha Toshiba
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