Patent
1995-02-28
1998-04-07
Robertson, David L.
395472, 395479, 395483, G06F 1300
Patent
active
057375755
ABSTRACT:
Memory access latency is reduced by storage of additional pages of a block together with storage protection keys in a cache memory. When a miss occurs for a particular address and/or a corresponding storage protection key in an address translation look-aside buffer, other storage protection keys for other pages of the same block containing the page causing the miss are associatively accessed from a multi-page key cache. Thus, pages which do not have addresses or storage protection keys stored in the translation look-aside buffer but which are locally stored in a cache may have the storage protection keys provided locally with short access time and without communication over a network.
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International Business Machines - Corporation
Robertson David L.
Samodovitz Arthur J.
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