Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – Frequency of cyclic current or voltage
Reexamination Certificate
1997-12-04
2001-06-12
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
Frequency of cyclic current or voltage
C324S076420, C324S076480
Reexamination Certificate
active
06246223
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to methods for measuring the frequency of periodic square pulse trains, and more particularly, to a method, for use on a parametric tester having a slow integration time and a slow delay time, to measure the output frequency of a ring oscillator through voltage sampling, which allows the output frequency of the ring oscillator to be more effectively and precisely measured.
2. Description of Related Art
A parametric tester is also referred as a wafer acceptance tester (WAT), which is basically composed of a probe station, a switch matrix, a voltage sourcing/measurement unit (SMU), and a computer means for control of the test programs and data acquisition. The parametric tester is widely used in semiconductor industry for the purpose of collecting lot-to-lot data that are used for statistical analysis on variations in the fabrication processes and performances of the fabricated semiconductor devices. The analysis can help engineers to optimize the design of process windows.
The parametric tester is also useful for measuring the output frequency of a ring oscillator which is fabricated on a semiconductor chip. The collected frequency data are related to the performance of the ring oscillator. One problem in the frequency measurements of ring oscillators is that the integration time and delay time are relatively lengthy, so as to make the measurement difficult to carry out.
FIG. 1
is a schematic block diagram of a system setup for a parametric tester (represented by a block indicated by the reference numeral
10
) to measure the output frequency of a ring oscillator (represented by a block indicated by the reference numeral
102
). The parametric tester
10
includes a switch matrix
108
and an SMU
110
. The ring oscillator
102
is a closed loop circuit composed of a series of inverters (not shown) capable of generating a signal (which is typically a periodical square pulse train) having output frequency
103
in a range from several kilohertz to several megahertz. The waveform with the output frequency
103
can be visualized by using an oscilloscope. The exact value of the output frequency
103
is dependent on the characteristics of the transistors used to constitute the ring oscillator
102
on the semiconductor chip. The on-chip ring oscillator is a useful tool for the calibration of transistor mode in circuit designs.
The signal with output frequency
103
is first transferred to a buffer
104
, and then to a frequency divider
106
that is capable of dividing the signal with output frequency
103
by a predetermined factor to obtain a reduced output frequency
107
. The frequency divider
106
is composed of a plurality of D-type flip-flops (not shown). A 7-decade frequency divider can down convert a 5 MHz (period is 210
−7
sec.) pulse train to a reduced frequency as low as 1 Hz.
The frequency-downconverted pulse train
107
is then transferred via the switch matrix
108
to the SMU
110
in the parametric tester
10
. The SMU
110
then measures the frequency of the received pulse train.
One drawback to the foregoing parametric tester, however, is that, at the start of the sampling process on the received pulse train, there will be an initial delay time T
d
and subsequently an integration time T
g
(which is equal to one sampling period), and both are larger than the rising/falling transition time T
r
of the received pulse train. For instance, in a typical case, T
d
is 5 msec (millisecond) and T
g
is 50 msec, while T
r
is 10 &mgr;sec (microsecond). Due to these two factors, even though the output frequency
103
from the ring oscillator
102
can be lowered by the frequency divider
106
to a reduced value of 1 Hz, it is nonetheless difficult for the parametric tester
10
to precisely measure the output frequency of the ring oscillator
102
.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a method for use on a parametric tester that allows the parametric tester to more effectively and precisely measure the output frequency of a ring oscillator.
In accordance with the foregoing and other objectives of the present invention, a method is provided for use of a parametric tester to more effectively and precisely measure the output frequency of a ring oscillator. The method is used on a parametric tester to measure the output frequency of a ring oscillator that outputs a periodic square pulse train.
In the first step, the ring oscillator generates a periodic square pulse train V
O
having a frequency f. This output frequency f is then transferred to a frequency divider.
In the second step, a suitable integer K is selected that causes the frequency divider to divide the output frequency f by a factor of 2
K
to obtain a frequency-downconverted pulse train V
K
. Subsequently, the frequency-downconverted pulse train V
K
is transferred to the SMU of the parametric tester.
In the third step, a sampling process is performed by the parametric tester on the frequency-downconverted pulse train to thereby obtain a series of sampled signals V
S
. Meanwhile, the integration time T
g
, delay time T
d
, and sampling period T
s
are registered. The sampling period T
s
is the total duration of the delay time Td and the integration time T
g
.
In the fourth step, the sampled signals are classified in accordance with their magnitudes into three states: a high-level state, an intermediate-level state, and a low-level state. The sampling process continues until at least two sampled signals at the intermediate-level state are obtained, which are respectively designated by M
1
and M
2
.
In the fifth step, a delta transition time T
1
for the first intermediate-level state is computed based on the magnitude of the first intermediate-level state M
1
, the integration time T
g
, and the maximum amplitude of the frequency-downconverted pulse train V
K
.
In the sixth step, a delta transition time T
2
for the second intermediate-level state is computed based on the magnitude of the second intermediate-level state M
2
, the integration time T
g
, and the maximum amplitude of the frequency-downconverted pulse train V
K
.
In the seventh step, the number N of pulse state transitions from one state to the other during the M
1
to M
2
period is counted.
In the eight step, the length of the M
1
to M
2
period is computed.
In the ninth step, the frequency f
L
of the frequency-downconverted pulse train V
K
is computed.
In the tenth step, the output frequency f of the ring oscillator under measurement is computed.
REFERENCES:
patent: 4142146 (1979-02-01), Schumann et al.
patent: 4651089 (1987-03-01), Haigh
patent: 4721855 (1988-01-01), Fazekas
patent: 4779044 (1988-10-01), Skolnick et al.
patent: 5084669 (1992-01-01), Dent
patent: 5095267 (1992-03-01), Merrill et al.
patent: 5529068 (1996-06-01), Hoenninger et al.
patent: 5530367 (1996-06-01), Bottman
patent: 5638005 (1997-06-01), Rajan et al.
Metjahic Safet
Nguyen Vincent Q.
Rabin & Champagne, P.C.
Winbond Electronics Corp.
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