Method of manufacturing integrated circuit devices

Details Method of manufacturing integrated circuit devices Method of manufacturing integrated circuit devices

1999-08-20

2001-03-27

Powell, William (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S724000, C438S744000, C438S745000

Reexamination Certificate

active

06207570

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of manufacturing semiconductor integrated circuit interconnect structures. The invention relates more particularly to 1) a method for removing barrier material that lies between copper conductors in damascene interconnections, and 2) a method for removing a thin layer (<200 Angstroms) of silicon nitride material that has been intentionally un-etched during the formation of trenches and vias in interconnect dielectric and thereby not exposing copper metal.
2. Background of the Invention
Semiconductor integrated circuit devices, or apparatuses, typically comprise silicon and multiple layers of vertically stacked metal interconnect layers with dielectric materials disposed between them. The fabrication of such apparatuses typically involves the repeated deposition or growth, patterning, and etching of thin films of semiconductor, metal, and dielectric materials.
Current interconnect processing uses metal etching to define the conductors and dielectric etching to define the vias. In future damascene interconnect processing, for which this invention is primarily intended, dielectric etching will be used to define both conductors and vias. The following discussion of dielectric etching also applies to metal etching used to define conductors.
A via or trench pattern etched into a single layer of dielectric that will be filled with a conducting metal material is known as a single damascene, and a “double” layer of dielectric containing a trench above a via that will be filled with a conducting metal material is known as a dual damascene. For example, a single damascene structure is shown in
FIG. 1 and a
dual damascene structure is shown in FIG.
2
. In
FIGS. 1 and 2
, during semiconductor fabrication, an etch-stop SiN layer
5
and
14
, respectively, is commonly used at the bottom of an etched low-k structure
3
and
12
, respectively, to prevent breakthrough to an underlying copper region
8
and
17
, respectively, and to permit over-etching to account for etch non-uniformity. When the exposed nitride layer
7
and
16
is finally plasma or RIE etched to expose copper region
8
and
17
, electrical damage to the gate can occur. There is also a tendency to sputter copper
8
and
17
onto adjacent areas of dielectric
4
and
13
that is not yet protected by barrier material.
For brevity, the remaining background involves only the single damascene structure of
FIGS. 3
,
4
, and
5
after etching the structure of FIG.
1
. As shown in
FIG. 3
, the sputtered copper
18
on the sidewall of low-k dielectric
4
can lead to leakage. Wet cleaning processes may be employed, but there is a tendency for the low-k dielectric
4
to absorb moisture, which can affect apparatus performance. Additionally, as wiring dimensions shrink to less than 0.2 &mgr;m, cleaning the bottom of high aspect ratio features becomes less efficient. After cleaning, the etched dielectric structure
3
that is formed, as shown in
FIG. 4
, is coated with a thin layer of barrier material
19
and the structure
3
is filled with copper metal
20
. The barrier material
19
between copper
20
and cap
2
is intended to prevent diffusion of copper into dielectric
4
and cap
2
, which can cause undesirable leakage between conductors. Copper
20
and barrier material
19
are polished and/or planarized and removed back to the cap
2
. Chemical mechanical polishing (CMP) is preferred to ideally form a polished, planar surface consisting essentially of copper metal areas isolated from each other by dielectric material. This structure is then ready for dielectric depositions for the next interconnect layer (via or via and trench). In practice, chemical mechanical polishing does not lead to an acceptable planar surface.
As chemical mechanical polishing proceeds, copper
20
is removed until the top surface barrier material
11
is exposed. Since the chemical and mechanical properties of barrier material and copper differ, copper is more easily removed than the harder, more chemically inert barrier material resulting in inconsistent removal of the two materials. Thus, a slight “dishing”
50
of copper
20
occurs, as shown in FIG.
5
. Since the barrier material
19
is also somewhat conducting, failure to completely remove it leads to barrier contamination
52
that can cause electrical leakage between copper conductors. In addition to leakage, chemical mechanical polishing of barrier material tends to magnify erosion and dishing of features, which introduces undesirable topography that is amplified as more layers are completed. This ultimately affects critical lithography steps in the upper layers. A highly selective dry process for removal of barrier material and etch-stop SiN after the low-k etch, once copper is removed, would be an effective method of minimizing the problems of copper sputtering, barrier contamination, dishing, and erosion.
A method is known for plasma etching of vias in which back sputtered metal residue on the walls of vias is removed during the dielectric etch. In this process, a gas capable of forming volatile compounds with the underlying metal is added to the fluorine-bearing gases. The volatile compounds are then easily evacuable. The “metal-scavenging” gases used in the process are gases such as Cl
2, HCl
2
, Br
2
, HBr and BCl
3
.
A method is known for removing etching residues by applying to the substrate surface a mixture of gases such as oxygen, nitrogen, fluorine, hydrofluorocarbon and fluorinated methane and amine gases to remove the photoresist layers and make the etching residues water-soluble. The residues are then rinsed away with deionized water.
A method is known for preventing etching residue deposits by stopping the injection of reactive gases to a dry etching reactor when the etch is nearly completed, while maintaining power to the reactor. The gases in the reactor are maintained in a plasma state. The reactive gas is then evacuated from the reactor before decreasing the power to the reactor. This process prevents the deposition of residue which forms from the etchant materials after power to the reactor is shut off when etchant byproducts are no longer receiving excitation from plasma state electron collisions.
A method is known for manufacturing a semiconductor apparatus in an atmosphere having a carbonless, chlorine-based gas or a mixture of a carbonless, chlorine-based gas and an inactive gas in order to remove contaminant which would promote reactivity with aluminum chemical gas deposition on the surface of the insulating layer.
A method is known for selectively etching a first region comprised of silicon, tantalum, tantalum silicide and tantalum nitride, relative to a second region comprised of tantalum oxide or silicon dioxide, where a polyatomic halogen fluoride vapor is used in the substantial absence of plasma. The polyatomic halogen fluoride is either BrF
5
, BrF
3
, ClF
3
, or IF
5
.
A method has been described, wherein polyatomic halogen fluorides were found to be effective and selective etchants for a variety of transition metals and metal compounds. In particular, ClF
3
is economically desired for the etching.
SUMMARY OF THE INVENTION
One aspect of the invention is a method of manufacturing an integrated circuit including the steps of: (1) providing an apparatus having a plurality of exposed metal-conducting regions adjacent to a plurality of dielectric regions, covered at least partially with a barrier material; (2) subjecting the apparatus to a reducing gas to reduce metal oxide on the metal-conducting regions to metal; (3) contacting the barrier material with XeF
2
to remove selected portions of the barrier material; (4) exposing the apparatus to a reducing gas to transform residual metal oxide and fluoride to metal at contacted surfaces; and preferably, (5) chemical mechanical polishing, or planarizing, portions of the metal-conducting regions that protrude beyond the adjacent dielectric regions to complete planarization after the barrier material has been remo

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