Ripple carry logic and method

Details Ripple carry logic and method Ripple carry logic and method

2000-06-02

2001-08-21

Wambach, Margaret R. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Shift register

Particular input circuit

C377S049000, C377S055000, C377S078000, C327S269000, C327S270000, C327S361000

Reissue Patent

active

RE037335

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to ripple-carry logic circuitry, and more specifically to method and apparatus for increasing the maximum achievable operating frequency of circuits employing ripple-carry logic elements.
BACKGROUND OF THE INVENTION
Conventional ripple-carry logic elements such as multipliers or adders of multi-bit applied numbers commonly impose delays in producing resultant outputs attributable to arrival at the ripple inputs at different time intervals of all the significant bits. Known attempts to circumvent such delays include performing partial arithmetic operations upon the significant bits of the numbers upon appearance at the inputs of the logic elements, and performing parallel processing of the multi-bit numbers buffered in input registers. Additionally, each significant bit of a number may be represented by other numbers (e.g., carry-save format), usually two-bits wide, for selective logic processing to reduce delays in producing the desired arithmetic logical output.
SUMMARY OF THE INVENTION
In accordance with the present invention, individual arithmetic logic stages that produce carry outputs for successive similar arithmetic logic stages each include input registers with substantially matching delay elements interposed between successive ones of the clock inputs of the registers for respective ones of the logic stages. In this manner, delays are attributable to successively latching the significant bits of input signal into respective input registers for the logic stages which are operable in substantially common clocking intervals to reduce overall effective delays in producing resultant arithmetic logical outputs.


REFERENCES:
patent: 5481582 (1996-01-01), Ibenthal
patent: 5488318 (1996-01-01), Vajapey et al.

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