Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
1999-08-05
2001-04-03
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
Reexamination Certificate
active
06211088
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a manufacturing method for a semiconductor gas-phase epitaxial wafer, having a silicon epitaxial layer, which is grown on a main surface of a wafer, and used as a substrate for circuit elements of LSI (large-scale integration). More specifically, the present invention relates to a manufacturing method for a semiconductor gas-phase epitaxial wafer. In which a two-sided polishing process, a wafer backside CVD film growth process, and a one-sided polishing process, which polishes the main surface, are performed when preparing a wafer for epitaxial growth, thereby achieving extremely outstanding flatness, and a large-diameter with particularly high precision, and therefore increasing the precision and quality of the silicon epitaxial layer grown thereafter.
DESCRIPTION OF THE PRIOR ART
The large-scale integration of silicon semiconductor devices is progressing with high speed, and the characteristics required of silicon wafers have become increasingly more demanding. For this kind of highly-integrated device, CZ silicon wafers, grown using the Czochralski (hereinafter referred to as CZ) process, have been used for some time now.
A CZ silicon wafer contains supersaturated interstitial oxygen in concentrations from (10~18)×10
17
atoms/cm
3
, and it is widely known that oxygen precipitates and crystal defects, which occur inside a wafer at a sufficient distance from the device active area, have a gettering effect on heavy metal impurities.
Meanwhile, in line with the downscaling of semiconductor devices, high-energy ion implantation has come to be used in the formation of a well diffusion layer, and the device process is being carried out at low temperatures of less than 100° C. so as to achieve shallow junction depth.
Consequently, there is not enough outward diffusion of oxygen, and it is becoming difficult to curb the generation of crystal defects in the device active area. This situation has led to the widespread use for today's high-integration devices of a silicon epitaxial wafer, which has a completely crystal defect-free, high-quality epitaxial layer grown on a CZ-Si substrate.
A semiconductor gas-phase epitaxial wafer manufacturing method for preparing the above-mentioned epitaxial wafer comprises; 1) a slicing process, which produces a thin, disk-shaped wafer by slicing a single-crystal ingot pulled in accordance with a single-crystal pulling apparatus; 2) an edge contouring process for preventing chips and cracks in a wafer; 3) a lapping process for making an edge-contoured wafer flat; 4) an etching process for removing a processing deformed layer generated in a wafer in accordance with the above-mentioned processing; 5) an edge-contoured portion polishing process, in which the edge-contoured portion of a wafer is finish polished; 6) a polishing process, in which either one side or two sides of the above-mentioned wafer is polished; and 7) a process, in which the above-mentioned wafer is finish polished.
Further, an epitaxial wafer is manufactured by growing, via gas-phase epitaxy, a lightly-doped epitaxial layer on the main surface of a heavily-doped single-crystal wafer. Thus, when heated at a high temperature in a hydrogen atmosphere, the backside of the wafer is etched by the hydrogen, and dopant, which was added in a high concentration, is effused. This dopant is incorporated into the epitaxial layer once again during epitaxial growth, a process known as the autodoping phenomenon.
In the past, in order to prevent the autodoping phenomenon, either a CVD film, in accordance with a CVD reactor, or a thermal oxide film was formed on the backside of a wafer for use in gas-phase epitaxy, so that the backside of the wafer would not be etched by the hydrogen in the gas-phase epitaxy apparatus.
Further, when a CVD film and thermal oxide film are formed on the backside of a wafer as described above, in accordance with the above-mentioned film being formed on the edge-contoured portion, the reactant gas comes in contact with the wafer peripheral surface in the epitaxial growth process, generating Si aggregates. This is a problem in that the aggregated silicon falls off the wafer surface in the semiconductor device fabrication process, becoming the cause of contaminants adhering to the wafer surface.
Accordingly, a method has been proposed (Japanese Patent Laid-open Nos. 9-199465 and 10-070080), whereby, after the formation of either a CVD film, or a thermal oxide film on the backside of a wafer, the above-mentioned film covering the edge-contoured portion is removed prior to epitaxial growth.
As described above, a gas-phase epitaxial wafer was manufactured using a large number of processes, including a method by which a CVD film and thermal oxide film were formed on the backside of a wafer that had undergone a variety of polishing processes and had been etched. Then the above-mentioned film covering the edge-contoured portion was removed ahead of time, and the main surface side subjected to one-sided polishing.
As for this gas-phase epitaxial wafer, the degree of flatness required in a wafer has become more stringent in line with the increasing level of integration of today's device processes, and plans for making wafers larger with diameters of 12 inches or more have made it difficult to achieve the flatness required using conventional manufacturing methods.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a manufacturing method for a semiconductor gas-phase epitaxial wafer, which achieves the extremely high wafer flatness demanded in line with making wafers larger in size and increasing the level of integration of the device processes, and for forming on the backside of a wafer either a CVD film or a thermal oxide film required for a gas-phase epitaxial wafer, and solving the problems related thereto, and more particularly, achieves the high degree of flatness, and low processing deformation required by large-diameter wafers, and enhances the yield in the device process.
The inventors, with the object of achieving a semiconductor wafer with a high degree of flatness and low processing deformation, and enhancing yield in the device process, carried out a variety of studies involving grinding and polishing processes in a manufacturing method for a semiconductor gas-phase epitaxial wafar, which enables a thin, disc-shaped wafer to be sliced from a single-crystal ingot, a required surface to be finished to a mirror surface, and an epitaxial layer to be formed on the main surface.
As a result, the inventors brought the present invention to completion based on the knowledge that introducing into the above-mentioned manufacturing method a two-sided polishing process for polishing both the front and back surfaces of a wafer; a process for forming either a CVD film or a thermal oxide film on the backside of a wafer; and a one-sided mirror-finish polishing process for polishing the main surface of a wafer enables the realization of the extremely high wafer flatness demanded by a large-diameter wafer, while preventing autodoping.
Further, the inventors learned that in the above-described manufacturing process, the two-sided polishing process can be replaced by a series of processes comprising a two-sided grinding process, a finish grinding process for finish grinding either one side or both sides of a wafer with a high degree of precision and low deformation, and an alkali cleaning process, providing the same working effect as the two-sided polishing process.
Furthermore, the inventors learned that in the above-described manufacturing process, it is possible to enhance yield in the device process by adding a process which removes that portion of the CVD film or thermal oxide film which was provided to the backside of a wafer, and which wrapped around to the front side of the wafer during growth, and was generated up to the edge-contoured portion of the wafer. For example, a process which removes the film from the edge-contoured portion by bringing an etchant-impregnated material in contact
Masuda Sumihisa
Sakai Masato
Breiner & Breiner
Lee Calvin
Smith Matthew
Sumitomo Metal Industries Ltd.
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