Semiconductor memory device having reduced interconnection...

Details Semiconductor memory device having reduced interconnection... Semiconductor memory device having reduced interconnection...

1999-02-16

2001-05-29

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S164000, C365S214000, C365S174000

Reexamination Certificate

active

06240006

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, particularly to an interconnection structure for reducing the resistance of interconnection lines arranged on a memory mat without increasing a memory mat area. The present invention more particularly relates to an interconnection structure for decreasing the resistance of interconnection lines located at the same layer as that of an interconnection line transmitting a memory cell selection signal.
2. Description of the Background Art
FIG. 17
schematically shows an entire structure of a conventional semiconductor memory device. In
FIG. 17
, a memory mat
1
having a plurality of memory cells MCs arranged in rows and columns is divided into a plurality of memory blocks MB#0-MB#n in a row direction. In each of memory blocks MB#0-MBn, a plurality of sub word lines SWLs placed corresponding to respective rows of memory cells MCs and having memory cells MCs of corresponding rows connected thereto, and a bit line pair BLP placed corresponding to each column of memory cells and having corresponding memory cells connected thereto are provided.
FIG. 17
illustrates representatively one sub word line SWL, one bit line pair BLP, and a memory cell MC arranged corresponding to a crossing of sub word line SWL and bit line pair BLP.
A main word line MWL extending in the row direction is commonly provided to memory blocks MB#0-MB#n. Main word line MWL is arranged corresponding to a prescribed number of sub word lines in each of memory blocks MB#0-MB#, with the prescribed number being one or more. A sub word line driver SWD is placed corresponding to each sub word line SWL. Each sub word line driver SWD drives a corresponding sub word line SWL into a selected state according to at least a signal potential on a corresponding main word line MWL. If main word line MWL is arranged corresponding to each row of memory blocks MB#0-MB#n, sub word line driver SWD drives a corresponding sub word line SWL into a selected state according to a signal potential on the corresponding main word line MWL. If main word line MWL is arranged corresponding to memory cells of a plurality of rows in memory mat
1
, sub word line driver SWD drives a corresponding sub word line SWL into a selected state according to a signal potential on the corresponding main word line MWL and a row address predecode signal (as discussed below).
The semiconductor memory device further includes a row selection drive circuit
2
driving main word line MWL placed corresponding to an addressed row into a selected state according to an address signal (not shown), a bit line equalize circuit
3
setting bit line pair BLP at a prescribed voltage in a standby state, a sense amplifier circuit
4
including a sense amplifier provided corresponding to each bit line pair BLP and differentially amplifying potential on the corresponding bit line pair BLP in an activated state, and a column selection circuit
5
selecting a bit line pair placed corresponding to an addressed column according to a column address signal (not shown). In a standby state, main word line MWL is in a non-selected state, and sub word lines SWLs in each of memory blocks MB#0-MB#n are also in a non-selected state. Bit line pair BLP is set (precharged and equalized) at a level of a prescribed voltage (an intermediate voltage between power supply voltage Vcc and ground voltage Vss) by bit line equalize circuit
3
.
When a memory cell selection cycle (active cycle) is started, row selection drive circuit
2
first drives main word line MWL corresponding to an addressed row into a selected state. Sub word line driver SWD drives a corresponding sub word line SWL into a selected state according to at least a signal potential on main word line MWL when the corresponding sub word line SWL corresponds to the addressed row. In each of memory blocks MB#0-MB#n, sub word line SWL placed corresponding to the addressed row is driven into a selected state. Accordingly, data stored in memory cell MC is transmitted onto bit line pair BLP.
Sense amplifier circuit
4
is then activated, data of memory cell MC read onto bit line pair BLP is sensed, amplified and latched. Data is written into or read from bit line pair BLP that corresponds to a column selected by column selection circuit
5
.
Word lines arranged corresponding to memory cell rows each have a hierarchical structure formed of main word line MWL commonly provided to a plurality of memory blocks MB#0-MB#n, and sub word line SWL to which memory cells MCs are connected in each of memory blocks MB#0-MB#n. It is possible to transmit a row select drive signal fiom row selection drive circuit
2
to the end of main word line MWL at a high speed since no memory cell MC is connected to main word line MWL. The number of memory cells MCs connected to sub word line SWL is small and accordingly the parasitic capacitance of sub word line is small. Therefore, the hierarchical structure of word lines formed of the main word lines and sub word lines allows a memory cell row to be driven into a selected state at a high speed even if the storage capacity of the semiconductor memory device is increased and the number of memory cells of one row increases.
FIG. 18
shows one example of a structure of sub word line driver SWD illustrated in FIG.
17
.
FIG. 18
shows sub word line drivers provided to a memory block MB#i (i=0-n). One main word line MWL is arranged corresponding to sub word lines SWLa-SWLd placed corresponding to
4
rows of memory cells in memory block MB#i. Sub word line drivers SWDa-SWDd are arranged corresponding to respective sub word lines SWLa-SWLd.
Sub word line drivers SWDa-SWDd are respectively enabled when a signal potential on main word line MWL is at a logical high or H level indicating a selected state, and drive corresponding sub word lines SWLa-SWLd into a selected state respectively according to row predecode signals Ra-Rd. One of row predecode signals Ra-Rd is driven into a selected state to designate one of sub word lines SWLa-SWLd.
The arrangement shown in
FIG. 18
allows one main word line MWL to be placed corresponding to memory cells of 4 rows to relax the pitch condition of main word lines MWLs. Consequently, main word line MWL can be arranged with a sufficient margin.
As an alternative to the structure shown in
FIG. 18
, decoders respectively enabled in response to a signal potential on main word line MWL to transmit row predecode signals Ra-Rd to corresponding sub word lines SWLa-SWLd may replace sub word line drivers SWDa-SWDd.
FIG. 19A
schematically shows a structure of one memory block of the semiconductor memory device illustrated in FIG.
17
.
FIG. 19A
shows a structure of a portion related to memory cells MCs arranged in two columns.
In
FIG. 19A
, memory block MB#i includes a plurality of memory cells MCs arranged in rows and columns, sub word lines SWLa, SWLB, . . . arranged corresponding to respective memory cell rows and having memory cells MCs of corresponding rows connected thereto, and a plurality of bit line pairs BLPa . . . BLPm arranged corresponding to respective memory cell columns and having memory cells of corresponding columns connected thereto. Bit line pair BLPa includes bit lines BLa and /BLa, and bit line pair BLPm includes bit lines BLm and /BLm. Memory cells MCs are arranged corresponding to crossings of bit line pairs BLPa . . . BPLm and sub word lines SWLa, SWLb, . . .
FIG. 19A
illustrates memory cells MCs arranged corresponding to respective crossings of sub word line SWLa and bit lines BLa and BLm, and memory cells MCs arranged corresponding to crossings of sub word line SWLb and bit lines /BLa and /BLm respectively.
Memory cell MC includes a memory capacitor MQ storing information, and an access transistor MT responsive to a signal potential on a corresponding sub word line SWL (SWLa or SWLb) to become conductive to connect memory capacitor MQ to a corresponding bit line BL

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