Electric power conversion systems – Current conversion – Including automatic or integral protection means
Utility Patent
1998-12-23
2001-01-02
Wong, Peter S. (Department: 2838)
Electric power conversion systems
Current conversion
Including automatic or integral protection means
C361S091800
Utility Patent
active
06169672
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a power converting apparatus using semiconductor devices.
While development of semiconductor switching devices having a higher withstand voltage and supplying a large current has been desired in order to meet the demands for power converting apparatuses of smaller size and with higher efficiency in recent years, there have been developed such large capacity devices as insulated-gate bipolar transistors (hereinafter briefly called IGBT) of a 3.3 kV-1.2 kA class and gate turn-off thyristors (hereinafter briefly called GTO) of a 6 kV-6 kA class.
FIG. 5
shows a conventional single-phase inverter using GTOs as semiconductor switches. This inverter supplies a load
10
with AC power converted from a DC power source
1
by alternately turning on-off the GTOs (
41
,
42
,
43
,
44
). Upon turning off of the GTOs at this time, energy stored in wiring inductance
2
and anode reactors (
31
,
32
,
33
,
34
) are changed into an overvoltage impressed on the GTOS. Therefore, there are generally provided snubber circuits for suppressing the overvoltage. Referring to
FIG. 5
, snubber diodes (
71
,
72
,
73
,
74
) and snubber capacitors (
91
,
92
,
93
,
94
) are connected in series with the anode reactors (
31
,
32
,
33
,
34
) and energy recovery circuits (
121
,
122
,
123
,
124
) for the snubber capacitors (
91
,
92
,
93
,
94
), through diodes (
111
,
112
,
113
,
114
), respectively. Accordingly, waveforms at the time of turn-off of the GTOs become as shown in FIG.
6
.
Concerning the maximum output of such an inverter, the maximum cutoff current while it is in rated operation is determined by such factors as the current supply condition and the loss characteristic cooling characteristic of the device or the like, whereas the maximum cutoff current when fault protection is made is determined within the range of the rated controllable current of the device.
On the other hand, concerning the voltages, the snubber circuit is arranged and the power source voltage are determined so that the transient overshoot voltage occurring at the time when the current is cut off upon occurrence of a fault may not exceed the rated withstand voltage of the device. Therefore, it is the practice today to lower the power source voltage close to half the withstand voltage of the device.
Under these circumstances, there is a method for suppressing an overvoltage, in an arrangement of a snubber circuit, which is formed of a snubber diode, a snubber capacitor, and a snubber resistor, connected in parallel with the main switching device, by connecting a voltage regulating diode in parallel with the snubber capacitor (Japanese Patent Laid-open No. Hei 7-143733).
In
FIG. 8
, there is shown an example of a relationship between a withstand voltage and operating loss of a semiconductor device. When the withstand voltage of a device is increased, it becomes necessary to increase the thickness of the semiconductor wafer and, hence, the on-time voltage increases. Therefore, the on-time steady loss increases in direct proportion to the withstand voltage. Meanwhile, since both the operating voltage and the tail current at the time of turn-off (refer to
FIG. 6
) increase, the switching loss increases virtually in direct proportion to the square of the withstand voltage. While the relative magnitude of the switching loss and the on steady-state loss varies with the current supply condition, providing the device with a higher withstand voltage is accompanied by an increase in the device area and in the package size, an increase in cooling power, and so on, in order that increase in such losses is prevented and cooling of the device is facilitated.
However, since, in the above described prior art, the transient overshoot voltage, occurring at the time when a fault is protected, is great, it is inevitable to lower the power source voltage of the device to a level close to half the withstand voltage, which was raised with much effort. For this reason, even though the converting apparatus is made larger in size, only a relatively small converted power could be obtained.
Further, when a snubber circuit is provided for suppressing the overshoot voltage, it is always accompanied by generation of a line inductance (
81
,
82
,
83
,
84
). The energy stored therein is eventually consumed by the GTO (
41
,
42
,
43
,
44
) as the main switching device, a flywheel diode (
51
,
52
,
53
,
54
), and the snubber diode (
71
,
72
,
73
,
74
). Further, the current flowing at this time produces resonation between the inductance (
81
,
82
,
83
,
84
) of the snubber wiring and the parasitic capacitance of the snubber diode (
71
,
72
,
73
,
74
) or the snubber capacitor (
91
,
92
,
93
,
94
), which impresses an excessive voltage on the GTO (
41
,
42
,
43
,
44
) and the snubber diode (
71
,
72
,
73
,
74
), invites an increase in the device loss, and causes breakdown of the device.
It is an object of the invention to suppress the overvoltage and oscillating voltage that are impressed on semiconductor devices used in a power converting apparatus to thereby make the power converting apparatus provide a higher output and operate with a higher reliability.
DISCLOSURE OF INVENTION
The power converting apparatus of the present invention comprises a group of semiconductor switches including at least one semiconductor switch. The group of semiconductor switches are connected to a pair of DC terminals having a DC potential. The DC terminals correspond, for example, to the junctions of a DC power supply with the main circuit of the power converting apparatus. Further, across the semiconductor switch, or between the DC terminals, of the power converting apparatus according to the invention, a clamping circuit is connected in parallel. By means of the clamping circuit, the voltage impressed on the semiconductor switch is clamped at a voltage higher than the voltage between the DC terminals and lower than the withstand voltage of the semiconductor switch.
According to the invention, even if the semiconductor switch turns off a larger current than in a rated operation at the time when failure protection of the power converting apparatus is made, the overshoot voltage to be impressed on the semiconductor switch is clamped at a voltage value lower than the withstand voltage of the semiconductor switch. Therefore, the withstand voltage of the semiconductor switch can be lowered and, hence, the loss in the semiconductor switch can be reduced. Further, the power source voltage for the power converting apparatus can be raised. Therefore, a power converting apparatus with a higher efficiency and the capability of a higher power output can be realized.
The power converting apparatus according to the invention comprises, besides the semiconductor switch, a snubber circuit connected in parallel therewith. The snubber circuit is provided for suppressing the dV/dt of the voltage impressed on the semiconductor switch to thereby protect the semiconductor switch from an overvoltage. The snubber circuit in the power converting apparatus according to the invention has a circuit consisting of a diode and a capacitor connected in series. Further, the diode or the capacitor in the snubber circuit, i.e., the snubber diode or the snubber capacitor, is provided with a diode, connected in parallel therewith, having a semiconductor substrate whose band gap is wider than that of silicon.
The diode having a semiconductor substrate with a band gap wider than silicon can be made smaller in size than a diode having whose semiconductor substrate is made of silicon and, therefore, the diode, when connected to the snubber circuit, does not increase the wiring inductance. Accordingly, the electromagnetic energy stored in the snubber circuit does not increase and, in addition, the energy is consumed by this diode. Therefore, any voltage and current oscillation occurring in the snubber circuit can be suppressed.
REFERENCES:
patent: 4282555 (1981-08-01), Svedberg
patent: 4554487 (1985-11-01), Ni
Iwasaki Takayuki
Kimura Shin
Yatsuo Tsutomu
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Laxton Gary L.
Wong Peter S.
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