Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1998-12-15
2001-04-03
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB
Reexamination Certificate
active
06211693
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to testability circuits. More specifically, this invention relates to testability for cascode circuits used as high voltage interfaces.
BACKGROUND OF THE INVENTION
Newer technology devices, e.g., CMOS devices, which utilize lower operating voltages, are becoming pervasive. Nevertheless, there is still a need to interface with older technology devices. These older devices typically have higher operating ranges, e.g., 4.5 V to 5.5 V which are generally higher than a single transistor can tolerate. In some cases, buffer circuits, designed to tolerate this higher voltage, are used to interface with these older devices. These high voltage tolerant buffer circuits, however, are inappropriate for some newer CMOS devices that are required to use level shifting to interface to the higher voltage levels.
Some of the lower voltage devices contain level shift outputs to interface with devices having higher operating voltages. These level shift outputs use transistors that tolerate five volts. Level shifting can also be accomplished using cascode transistors to maintain acceptable voltage stress levels on the switching transistors. If, however, a cascode transistor is faulty, e.g., has a drain to source short, then the switching transistor will, generally, fail due to voltage stress. Conventional cascode design does not allow a faulty cascode device to be readily detected. Thus, although a conventional cascode configuration will likely perform appropriately during testing, it will fail prematurely in the field due to voltage overstress.
SUMMARY OF THE INVENTION
Therefore, a need has arisen for a testability circuit for cascode devices used in high voltage interface circuits. A testability circuit according to the present invention enables a determination to be made as to whether internal cascode transistors are operating properly before they enter the field.
According to one embodiment of the present invention, a level shifting circuit having a testability network is disclosed. The level shifting circuit includes a cascode configuration of active devices and a bias network arranged to bias the cascode configuration. The cascode configuration includes at least a first switching transistor and a second switching transistor and a first cascode transistor and a second cascode transistor arranged to limit voltage stress on said first and second switching transistors. A test network is connected to the cascode configuration and the bias network such that it provides an indication of a short circuit in one or both of the cascode transistors.
According to another embodiment of the present invention a testability circuit for cascode devices is disclosed. The testability circuit includes at least one test transistor pair, and a biasing transistor pair. Each test transistor pair comprises a first test transistor and a second test transistor. The drain of the first test transistor is connected to the source of the second test transistor, and the source of the first test transistor is connected to the drain of the second test transistor. The biasing transistor pair comprises a first biasing transistor and a second biasing transistor connected to the first and second test transistors of one test transistor pair to limit voltage stress on said first and second test transistors. When one of said test transistor pairs is connected to a cascode circuit arrangement, the testability circuit according to this embodiment provides an indication of a fault in said cascode circuit arrangement.
The above-described embodiments of the present invention provide various technical advantages. For example, the testability circuit according to the above-described embodiments provides the technical advantage of allowing the cascode devices to be tested. In addition, the testability circuits according to the above-described embodiments increase the reliability of level shifting circuits which use cascode devices helping to ensure that such level shifting circuits do not fail prematurely in the field. Other technical advantages are apparent to one skilled in the art from the following figures, description and claims.
REFERENCES:
patent: 4680486 (1987-07-01), Price et al.
patent: 5821799 (1998-10-01), Saripella
patent: 5995010 (1999-11-01), Blake et al.
patent: 6005415 (1999-12-01), Solomon
Andresen Bernhard H.
Wall Frederick G.
Brady III W. James
Marshall, Jr. Robert D.
Metjahic Safet
Tang Minh
Telecky , Jr. Frederick J.
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