Coating processes – Electrical product produced – Condenser or capacitor
Reexamination Certificate
1999-01-12
2001-03-13
Beck, Shrive (Department: 1762)
Coating processes
Electrical product produced
Condenser or capacitor
C427S080000, C438S239000, C438S253000
Reexamination Certificate
active
06200629
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of manufacturing a capacitor. More particularly, the present invention relates to a method for forming a stack of multi-layer metal capacitors.
2. Description of Related Art
Most analog or mixed mode circuits in a semiconductor chip contain capacitors. At present, most capacitors are of the double-polysilicon capacitor (DPC) type as shown in FIG.
1
. As shown in
FIG. 1
, a double-polysilicon capacitor
100
is a capacitor having an upper electrode
104
and a lower electrode
102
, both fabricated from polysilicon material. There is a dielectric layer
106
between the upper electrode
104
and the lower electrode
102
. N-type impurities, for example, can be doped into the polysilicon layer to increase its electrical conductivity. In general, the lower electrode
102
of the double-polysilicon capacitor
100
is connected to a ground terminal while the upper electrode
104
is connected to a negative bias voltage V
bias
. Hence, when the capacitor
100
is being charged, holes within the polysilicon lower electrode
102
migrate to a region on the upper surface of the lower electrode due to the negative bias voltage V
bias
. These holes compensate for the N-type impurities originally doped inside the polysilicon electrode
102
. Consequently, a depletion region
108
is formed on the upper surface of the electrode
102
, thus forming an additional dielectric layer. In other words, an additional dielectric layer is formed over the original dielectric layer
106
, thereby thickening the overall dielectric layer and reducing the charge storage capacity of the capacitor. Furthermore, capacitance of the capacitor is unstable due to some minor fluctuation of the negative bias voltage V
bias
too.
In addition, the double-polysilicon capacitor is formed by providing a first polysilicon layer, and then depositing a dielectric layer over the first polysilicon layer. Finally, one more polysilicon deposition process has to be carried out. The entire fabrication process is long and involves many steps. Moreover, conventional capacitor structure tends to occupy a larger chip area, thereby compromising the effort to increase the level of integration through a reduction in device dimensions.
In light of the foregoing, there is a need to provide an improved capacitor structure.
SUMMARY OF THE INVENTION
Accordingly, the purpose of the present invention is to provide a method for manufacturing a capacitor capable of preventing a reduction in storage capacity due to a thickening of the dielectric layer when bias voltage is applied to the capacitor during operation.
In another aspect, the purpose of the invention is to provide a simpler method of forming the capacitor, which method is capable of shortening processing time and reducing production cost. Furthermore, the capacitor formed by this method has a structure that occupies less space, and thereby is capable of increasing the level of device integration.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for manufacturing a capacitor. The method includes the steps of forming a dielectric layer over a substrate, and then forming at least one contact within the dielectric layer. Next, a first metal layer is formed on the dielectric layer and an electromigration layer is formed on the first metal layer. A patterned capacitor dielectric layer is formed on the electromigration layer in a capacitor area. A second metal layer is then formed over the substrate and defined, therefore a portion of second metal serving as an upper electrode of the capacitor is formed on the electromigration layer. A portion of the second metal layer on the contact serves as a portion of the via of the interconnects. The electromigration layer is self-alignedly patterned when patterning the second metal layer and a portion of the electromigration layer that serves as a lower electrode of the capacitor. The electromigration layer on the contact in the via area is used to prevent electromigration.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 2389420 (1945-11-01), Deyrup
patent: 2759854 (1956-08-01), Kilby
patent: 3718565 (1973-02-01), Pelletier
patent: 4436766 (1984-03-01), Williams
patent: 4453199 (1984-06-01), Ritchie et al.
patent: 5300307 (1994-04-01), Frear et al.
patent: 5685968 (1997-11-01), Hayakawa et al.
patent: 5913126 (1999-06-01), Oh et al.
patent: 5918135 (1999-06-01), Lee et al.
patent: 5920775 (1999-07-01), Koh
Beck Shrive
Strain Paul D.
Thomas Kayden Horstemeyer & Risley
United Microelectronics Corp.
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