Semiconductor device manufacturing: process – Avalanche diode manufacture
Reexamination Certificate
1998-08-05
2001-03-06
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Avalanche diode manufacture
C257S481000
Reexamination Certificate
active
06197649
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to processes for the manufacture of semiconductor devices and, more specifically, to a fast recovery diode (FRED) that is manufactured using a reduced number of masking steps.
Typically, the process for fabricating a FRED requires four or five masking steps. A first masking step defines the termination and P-type anode regions. A second masking step defines the contact region, and then a third masking step defines the deposited metal. Subsequently, a passivation layer is defined using a fourth masking step. Additionally, further masking steps may be incorporated for defining an equipotential ring (EQR) as well as for defining an enhancement termination implant.
Each of these masking steps may include a critical mask alignment, which adds manufacturing time and expense. Furthermore, each of the masking steps provides a possible source of device defects, as are caused by particles attached to the mask from the photoresist.
It is therefore desirable to minimize the number of critical alignments necessary as well as to reduce the number of masking steps to improve the manufacturing yield and reduce the manufacturing cost.
SUMMARY OF THE INVENTION
The present invention provides a novel process for the manufacture of vertical conduction fast recovery diodes in which only two or three masking steps are used. Only two masking steps are needed for manufacturing devices having a breakdown voltage rated at less than 800 volts. For higher voltage rated devices, an additional masking step is used to define the passivation layer. The FRED may be manufactured using localized oxidation of silicon (LOCOS) or using deposited low temperature oxide (LTO).
According to an aspect of the invention, a semiconductor device is fabricated by first forming at least one layer of first insulation material atop an upper surface of a silicon substrate which is of one conductivity type. Impurities of another conductivity type are then introduced into the upper surface of the silicon substrate. Selected regions of the first insulation material are patterned and etched away to form openings which expose underlying regions of the upper surface of the silicon substrate, and localized oxide regions are formed in the underlying regions. The layer of first insulation material is then removed to expose remaining unoxidized regions of the silicon substrate. An upper conductive layer is deposited, and selected regions of the layer are patterned and etched away to form openings which expose a bordering portion of the silicon substrate. Impurities of the one conductivity type are introduced into the openings of the bordering portion to form equipotential rings.
According to another aspect of the invention, a semiconductor device is fabricated by first forming at least an upper layer of insulation material on at least the upper surface of a silicon substrate of one conductivity type. Selected regions of the insulation material are patterned and etched away to form openings therein which expose underlying regions of the upper surface, and impurities of another conductivity type are introduced into the underlying regions to form diffused regions. An upper conductive layer is deposited, and selected regions thereof are patterned and etched away to form openings which expose at least bordering regions of the upper surface of the silicon substrate. Impurities of the one conductivity type are introduced into the bordering regions to form at least one equipotential ring.
REFERENCES:
patent: 4692995 (1987-09-01), Blanchard
patent: 5091332 (1992-02-01), Bohr et al.
patent: 5250449 (1993-10-01), Kuroyanagi et al.
patent: 5451544 (1995-09-01), Gould
patent: 5719421 (1998-02-01), Hutter et al.
patent: 5837378 (1998-11-01), Mathews et al.
S. Wolf, Silicon Process for the VLSI Era, vols. 1-2, (Lattice Press, California, 1986 and 1990).
S. M. Sze, Physics of Semiconductor Devices, (John Wiley & Sons, New York, 1981), p. 64.
Francis Richard
Ng Chiu
Elms Richard
International Rectifier Corp.
Ostrolenk Faber Gerb & Soffen, LLP
Wilson Christian D.
LandOfFree
Process for manufacturing planar fast recovery diode using... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for manufacturing planar fast recovery diode using..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for manufacturing planar fast recovery diode using... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2516533