Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-01-13
2001-01-30
Hjerpe, Richard A. (Department: 2774)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S100000
Reexamination Certificate
active
06181312
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to drive circuit for an active matrix liquid crystal display (LCD) device.
(b) Description of the Related Art
LCD devices now in widespread use are of an active matrix type in which thin film transistors (referred to as TFTs, hereinafter) are integrated as active elements in respective pixel elements. TFTs are generally classified into two types including amorphous silicon TFTs and polysilicon TFTs based on the semiconductor materials used therein.
In an LCD device using polysilicon TFTs having a high current driving capability, the polysilicon TFTs can be also provided in the peripheral circuits, thereby allowing the peripheral circuits to be disposed on the same substrate for the LCD device to achieve the advantage of a smaller circuit scale. Such an LCD device having peripheral circuits integrated therewith on the same substrate is called a drive circuit integrated LCD. A drive circuit integrated LCD device includes a data driver and a gate driver as peripheral circuits. The data driver drives data lines connected to source terminals of the TFTs in the pixel elements, whereas the gate driver drives gate lines connected to the gate terminals of the TFTs in the pixel elements. The drive circuit integrated LCD devices are widely used for liquid crystal (LC) projectors in which a compact circuit scale and a high-definition image quality are required.
In accordance with the increasing variety of image signal sources in recent years, LC projectors are expected to have a multi-scan function for displaying image signals of wide frequency bands. Therefore, the driver circuits should have the mutli-scan function in the drive circuit integrated LCDs for use in (LC) projectors.
An LCD device differs from a CRT in that the number of pixel elements cannot be changed in the LCD device depending on the image signals supplied thereto. In the LCD device, therefore, a picture image is generally displayed on a number of pixel elements fewer than the number of all the pixel elements provided in the LCD. In this case, the mutli-scan function is commonly realized according to either of the following two methods. In a first method, the image signal is displayed on a part of the display area, In a second method, the number of pixel elements for a picture image is modified at the same ratio i both longitudinal and lateral directions of the display area, thereby approaching the number of pixel elements displaying at that time to the total number of the pixel element provided in the LCD device. The present invention relates to the first method.
FIG. 1
shows a typical display area for explaining the first display method. The display area includes 1280 (horizontal)×1024 (vertical) pixel elements on the screen. The figure also shows a central picture area based on the SVGA standard, one of the display standards in personal computers. The central picture area includes 800 (horizontal)×600(vertical) pixel elements. This means that the picture image is displayed on the 800×600 pixel elements in the central area of the display, and the peripheral area is displayed in black color by preventing the light transmission in the non-display peripheral area.
An active matrix LCD is generally driven by a normally white mode of TN (twisted nematic) LC so as to improve its contrast ratio. The normally white mode is a known driving method in which light is transmitted through a LC pixel element when a voltage is not applied thereto. In order to display the black color in the normally white driving method, a black signal for displaying black color must be written into the peripheral areas during vertical blanking periods, i.e., periods when a picture image is not displayed. The vertical blanking period lasts only a short time, about 4 millisecond (msec.) for example, This causes a problem in that it is difficult to write all the signals for displaying the black color into desired areas during the vertical blanking period.
Patent Publication JP-A-8-122747 proposes a driving method for solving the aforementioned problem. In the proposed driving method, a gate driver circuit is operated in a high speed during the vertical blanking periods so as to write the black data into all the peripheral areas simultaneously.
FIG. 2
is a circuit diagram for showing a gate driver circuit having a function of writing the black data simultaneously into the top and bottom peripheral areas illustrated in FIG.
1
. The gate driver circuit includes a scan circuit A
1
having transfer elements A
1
1
-A
1
N
connected in N stages, and N decode units A
4
each disposed for a corresponding one of the transfer elements A
1
1
-A
1
N
in the scan circuit A
1
. Each of the decode units A
4
includes four NAND gates A
41
and four inverters A
42
. In the scan circuit A
1
, a start pulse SP is received ill synchrony with a clock signal CLK, and the data held by the first stage transfer element A
1
1
is shifted one stage by one stage from the left toward the right of the scan circuit A
1
. In the decode units A
4
, each of the outputs from the transfer elements A
1
1
-A
N
of the respective stages in the scan circuit A
1
is divided into four pulses based on M (eight, in this case) decode signals DC
1
-DC
8
.
FIG. 3
shows a timing chart of the gate driver circuit shown in
FIG. 2. A
frame period Tf is divided into a first period Tnm for displaying a picture image and a second period Tbw for writing data into the black color areas including the top and bottom peripheral areas.
In the first period Tnm, the scan circuit A
1
is synchronized with a clock signal CLK having a period which is fourfold the period of the horizontal synchronizing signal for the image signal Vsig to receive the start pulse SP in the scan circuit A
1
, whereby outputs S
1
-S
N
shown in the figure are obtained. Doing the first period Trim, image signals are written in a picture writing period Ta, during which decode signals DC
1
-DC
8
are supplied. Thus, respective signals of the outputs S
a+1
-S
b
which assume a high level within the period Ta are quartered based on the decode signals DC
1
-DC
8
, thereby outputting pulses sequentially through the output terminals G
4a+1
-G
4b
. In addition, by equalizing the respective pulse widths of the decode signals DC
1
-DC
8
with one horizontal period, the widths of the respective pulses delivered from the output terminals G
4a+1
-G
4b
are equalized with one horizontal period. With these pulses, the gate lines are driven to write the picture data.
FIG. 4
is an enlarged timing chart showing the second period Tbw shown in FIG.
3
. In the second period Tbw, the clock signal CLK is changed to have a frequency which is three or more digits higher than the frequency of the horizontal synchronizing signal, and a start pulse SP of a smaller pulse width is supplied. In the second period Tbw, delivery of the clock signal CLK is stopped for a clock signal stop period Tw after supplying a number of clock pulses equal to the number of the stages of the transfer elements A
1
1
-A
1
N
in the scan circuit A
1
. Here, in the respective stages of the transfer elements A
1
1
-A
1
N
in the scan circuit A
1
, the outputs S
1
-S
a
and S
b+1
-S
N
assume a high level, and the outputs S
a+1
-S
b
assume a low level. Since a high level of the decode signals DC
1
-DC
8
is supplied during the clock signal stop period Tw, all the outputs of the is decode units A
4
connected to the outputs S
1
-S
a
and S
b+1
-S
N
assume a high level. Subsequently, N or more clock pulses are supplied so that the outputs of all the transfer elements A
1
1
-A
1
N
in the scan circuit A
1
assume a low level.
In the following description of the drive circuit of
FIG. 2
, it is assumed that the stage number N of the transfer elements in the scan circuit A
1
is 256, “a” is 53, and “b” is 203, for example. In the first period Tnm, gate lines G
(4×53+1)
-G
(203×4)
, that is, 600 gate lines G
213
-G
812
are sequentially activ
Eisen Alexander
Hayes, Soloway, Hennessey Grossman & Hage, P.C.
Hjerpe Richard A.
NEC Corporation
LandOfFree
Drive circuit for an active matrix liquid crystal display... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Drive circuit for an active matrix liquid crystal display..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Drive circuit for an active matrix liquid crystal display... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2516247