Memory circuit

Details Memory circuit Memory circuit

1996-01-18

1999-05-11

Tu, Trinh L.

Excavating

371 211, 365201, G06F11/00

Patent

active

059035820

ABSTRACT:
In a semiconductor memory having a configuration of a plurality of bits, there are provided a parity calculation circuit and a test input-output circuit, wherein the test input-output circuit is operated during a pellet checking operation, outputs the test data inputted from a test input-output terminal to data buses while being divided into a plurality of bits constituting one unit during the writing operation, and then the same test data is written into the memory cell of a plurality of bits at the specified address. During the reading operation, a parity calculation circuit performs the parity calculation with all the readout data of a plurality of bits constituting one unit to generate the parity bit and the test input-output circuit outputs the parity bit from the test input-output terminal. The memory tester determines whether the value of the parity bit coincides with the expected output value, thereby the number of concurrent measurements in the pellet checking in the memory can be increased and the measuring cost is reduced.

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patent: 5218691 (1993-06-01), Tuma et al.
patent: 5448578 (1995-09-01), Kim

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