Method of forming a self-aligned contact hole on a...

Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching

Reexamination Certificate

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Details

C438S304000, C438S305000, C438S637000, C438S279000, C438S701000, C438S696000

Reexamination Certificate

active

06261968

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a self-aligned contact hole on a semiconductor wafer, and more particularly, to a method of forming a self-aligned contact hole of a DRAM (dynamic random access memory) on a semiconductor wafer.
2. Description of the Prior Art
In semiconductor fabrication, a contact hole is used to form an interconnect that electrically connects together devices of an integrated circuit. Generally speaking, a photolithographic and an etching process are performed on a semiconductor wafer to form a contact hole. However, as the line width of semiconductor designs shrinks, the size of the contact hole must also shrink. Current semiconductor fabrication techniques employ the differing etching selectivity of different materials in an etching process to form the self-aligned contact hole.
Please refer to
FIG. 1
to FIG.
3
.
FIG. 1
to
FIG. 3
are cross-sectional diagrams of forming a self-aligned contact hole
34
on a semiconductor wafer
10
according to the prior art. The semiconductor wafer
10
comprises a silicon substrate
12
, two gates
24
positioned on the surface of the silicon substrate
12
, a doped area
14
positioned between the gates
24
on the substrate
12
and a dielectric layer
28
of silicon oxide positioned on the silicon substrate
12
. The dielectric layer
28
covers the gates
24
. Each of the gates
24
comprises a gate oxide layer
16
of silicon oxide, a doped poly-silicon layer
18
and a silicide layer
20
. Each gate
24
also comprises a silicon nitride spacer
26
on each of two opposite walls, and a silicon nitride cap layer
22
on the top surface of the gate
24
.
According to the prior art, a spin coating process is performed to form a photoresist layer
30
on the dielectric layer
28
, and a lithographic process is then performed to form a pattern
32
in the photoresist layer
30
to define the size and the position of the contact hole
34
, as shown in
FIG. 2. A
dry etching process is performed, using the photoresist layer
30
as a hard mask, to remove the dielectric layer
28
under the pattern
30
down to the surface of the doped area
14
. A photoresist stripping process is then performed to totally remove the photoresist layer
30
so as to form the contact hole
34
, as shown in FIG.
3
.
When performing a self-aligned contact hole etching according to the prior art, the etching selectivity difference between silicon oxide and silicon nitride is exploited to form the contact hole
34
. The etching rate of the etching process is controlled to remove the silicon oxide dielectric layer
28
faster than the silicon nitride spacers
26
so as to remove only the dielectric layer
28
while keeping the spacers
26
. However, as the line width of the semiconductor design shrinks, the height of gate
24
becomes relatively larger in comparison to the line width. In order to reduce the contact resistance between the doped area
14
and a subsequently formed conductive plug in the contact hole
34
, the thickness of the spacers
26
is reduced so as to increase the contact area between the doped area
14
and the contact hole
34
. During the dry etching process the spacers
26
are damaged, particularly at the junction of the spacers
26
and the cap layer
22
, due to their extreme thinness.
The damage of the cap layer
22
and the spacers
26
affects the subsequent structure of the gates
24
. For example, the distance between the gates
24
and the conductive material that is used to fill the contact hole
34
becomes too short. This causes short-circuiting and electrical leakage between the conductive material in the contact hole, the doped poly-silicon layer
18
and the silicide layer
20
.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method of forming a self-aligned contact hole on a semiconductor wafer that avoids the above-mentioned problems.
In a preferred embodiment, the present invention provides a method of forming a self-aligned contact hole on a semiconductor wafer. The semiconductor wafer comprises a substrate, two gates positioned on the substrate, at least a doped area between the gates on the substrate and spacers on each of two opposite walls of each gate, the method comprising:
forming a dielectric layer on the surface of the semiconductor wafer, the dielectric layer covering the gates and the spacers;
performing a first etching process to remove the dielectric layer above the doped area down to a predetermined depth to form an opening, the bottom of the opening comprising the spacers and an upper portion of the gates;
forming poly-silicon spacers on the interior walls of the opening, the poly-silicon spacers covering an upper portion of the spacers and the upper portion of the gates; and
performing a second etching process to remove from between the poly-silicon spacers both the dielectric layer and a lower portion of the spacers down to the surface of the doped area so as to complete the self-aligned contact hole.
It is an advantage of the present invention that the etching process damage to the cap layer is effectively prevented by utilizing the high etching selectivity between poly-silicon and silicon nitride. Moreover, according to the present invention, it is not necessary to form spacers between the gates, simplifying the formation of the contact hole.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.


REFERENCES:
patent: 5554557 (1996-09-01), Koh
patent: 5851893 (1998-12-01), Gardner et al.
patent: 6033962 (2000-03-01), Jeng et al.
patent: 6037211 (2000-03-01), Jeng et al.
patent: 6146946 (2000-11-01), Wang et al.

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