Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Reexamination Certificate
2000-10-16
2001-09-04
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
C438S462000
Reexamination Certificate
active
06284620
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a method for fabricating an SOI (Silicon On Insulator) wafer for low-impedance high-voltage semiconductor components.
Dielectrically isolated (DI) epitaxial wafers are desirable for a variety of semiconductor components in order to ensure reliable insulation of adjacent components. Single-chip converters are one example thereof.
DI epitaxial wafers have been obtainable heretofore with a thickness of about 20 &mgr;m. However, epitaxial wafers which have a thickness exceeding 20 &mgr;m and, moreover, are dielectrically isolated would be advantageous for a wide variety of application purposes such as, by way of example, for obtaining a particularly high dielectric strength. Such DI epitaxial wafers are SOI wafers, for example, in which one or more epitaxial layers are applied on a substrate.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for fabricating an SOI wafer for low-impedance high-voltage semiconductor components, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known methods of this general type and in which the wafer has a layer thickness of more than 20 &mgr;m.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating an SOI wafer for low-impedance high-voltage semiconductor components, which is achieved through the use of the following steps:
(a) A first semiconductor wafer is produced from a semiconductor substrate, on one outer surface of which at least one epitaxial layer is provided.
(b) First trenches are introduced into the at least one epitaxial layer and a marking groove is introduced through the at least one epitaxial layer. The marking groove reaches the semiconductor substrate.
(c) A first layer, which is doped with a dopant of a first conduction type, is deposited on a surface of the at least one epitaxial layer, the first trenches and the marking groove.
(d) A first surface of the at least one epitaxial layer, which is provided with the doped first layer, is direct-bonded with an outer surface of a second semiconductor wafer. The outer surface of the second semiconductor wafer is provided with an insulating layer. The semiconductor substrate is removed from its other outer surface, which is opposite to the first surface, until the bottom of the marking groove is reached.
(e) Second trenches are introduced into the at least one epitaxial layer from the removed surface until the bottom of the first trenches is reached. A second layer, which is doped with a dopant of the first conduction type, is applied on walls of the second trenches so as to produce continuous trenches having walls that are provided with layers which are doped with dopant of the first conduction type.
(f) The continuous trenches are filled with insulating material.
In accordance with another mode of the invention, polycrystalline silicon which is heavily doped with dopant of the first conduction type is advantageously used for the first layer as well as for the second layer and thus for the layers which are doped with dopant of the first conduction type and are applied on the walls of the continuous trenches. However, instead of polycrystalline silicon, it is also possible to use monocrystalline silicon which is likewise heavily doped with dopant of the first conduction type.
In accordance with a further mode of the invention, the insulating material which fills the continuous trenches and, if appropriate, the marking groove as well, is preferably silicon dioxide. It goes without saying, however, that other insulating materials are also possible, such as, for example, silicon nitride or different layers made of silicon dioxide and/or silicon nitride.
In accordance with an added mode of the invention, it is particularly important that floating, island-like semiconductor regions of the second conduction type are introduced into the first semiconductor wafer made from the semiconductor substrate and the at least one epitaxial layer between the semiconductor substrate and the at least one epitaxial layer. If there is a plurality of epitaxial layers, such floating semiconductor regions of the other conduction type are also situated between the individual epitaxial layers. These floating regions may, if appropriate, also be connected in a grid-like manner.
The floating regions are preferably p-doped, so that the semiconductor substrate and the epitaxial layers are n-doped. The doping concentration of the floating regions is chosen to be high enough to ensure that the doping of the floating regions at least corresponds to the doping of the epitaxial layers or of the semiconductor substrate or else is higher than that doping.
In accordance with an additional mode of the invention, the doping per unit area in the floating regions is preferably above 10
12
cm
−2
.
Due to the floating regions, the semiconductor substrate and the at least one epitaxial layer can be doped more heavily with dopant of the first conduction type, with the overall result that a low-impedance wafer is obtained. When a voltage is applied to the wafer, the space charge zone builds up firstly as far as the first plane of the floating regions, that is to say as far as the interface between the uppermost and second-uppermost epitaxial layer and then remains in this plane. This build up of space charge zones progresses from plane to plane, which means that overall, if there are three planes, for example, four times the dielectric strength of a semiconductor wafer without floating regions is achieved. A semiconductor wafer provided with such floating regions is thus particularly suitable for low-impedance high-voltage semiconductor components.
In accordance with yet another mode of the invention, instead of the floating regions, it is also possible, if appropriate, to use homogeneous epitaxial layers, if less value is placed on the dielectric strength given a low resistivity.
In accordance with a concomitant mode of the invention, if appropriate, in addition to the floating regions, trenches with a pn junction (“junction trench”) can also be introduced into the epitaxial layers, if the intention is to fabricate especially space-saving semiconductor components.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for fabricating an SOI wafer for low-impedance high-voltage semiconductor components, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 5700712 (1997-12-01), Schwalke
patent: 5952694 (1999-09-01), Miyawaki et al.
patent: 19816449A1 (1999-10-01), None
patent: 61-182242 (1986-08-01), None
patent: 4348544 (1992-12-01), None
Bowers Charles
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Stemer Werner H.
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