Method of fabricating a dynamic random access memory capacitor

Details Method of fabricating a dynamic random access memory capacitor Method of fabricating a dynamic random access memory capacitor

1998-10-27

2001-01-09

Fahmy, Wael (Department: 2822)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C438S253000, C438S254000, C438S397000

Reexamination Certificate

active

06171924

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of fabricating a Dynamic Random Access Memory (DRAM) capacitor.
2. Description of Related Art
As a function of a microprocessor becomes more powerful, the program and calculation of software becomes more complicated, and thus the need for DRAM storage memory is increased. As the number of semiconductor elements incorporated in integrated circuit increases, a memory cell, which comprises a transfer field effect transistor (TFET) and a storage capacitor, is widely used. In
FIG. 1
, it is a circuit diagram of a DRAM memory cell. A capacitor C is selected from an array of capacitors used to store information as binary data by charging or discharging the capacitor. Normally, a binary bit is stored in each capacitor. Logic “0” is represented by the discharged state of the capacitor C, whereas logic “1” is represented by the fully charged state of the capacitor C. In general, a dielectric layer
101
is deposited between a top electrode (cell electrode)
102
and a bottom electrode (storage electrode)
100
. The capacitor C is electrically coupled with a bit line BL. The read/write operations of a DRAM memory cell are performed by the charged/discharged states of the capacitor C. The bit line BL is connected to the drain of a transfer field effect transistor T. The capacitor C is connected to the source of the transfer field effect transistor T. A signal is transmitted through a gate of the transfer field effect transistor T, which is used to control the capacitor C to turn on or turn off the connection with the bit line BL. In other words, the transfer field effect transistor T acts as a switch to control the charged or discharged state of the capacitor C.
In the DRAM manufacturing process, a two-dimensional capacitor called a planar-type capacitor is mainly used for a conventional DRAM having a storage capacity less than 1M (mega=million) bits. In the case of a DRAM having a memory cell using a planar type capacitor, electric charges are stored on the main surface of a semiconductor substrate, and thus the main surface is required to have a large area. This type of a memory cell is therefore not suited to a DRAM having a high degree of integration. For a highly integrated DRAM, such as a DRAM with more than 4M bits of memory, a three-dimensional capacitor, such as a stacked-type or a trench-type capacitor, has been introduced.
With stacked-type or trench-type capacitors, it has been made possible to obtain a larger memory within a similar volume. However, a capacitor with such a simple three-dimensional structure as the conventional stacked-type or trench-type is insufficient for a semiconductor device of an even higher degree of integration, such as a very-large-scale integration (VLSI) circuit having a capacity of 64M bits.
One solution for improving the capacitance of a capacitor is to use a fin-type stacked capacitor. The fin-type stacked capacitor includes electrodes and dielectric layers which extend in a fin shape in a plurality of stacked layers. Hence, the surface area of the electrode is enlarged while the capacitance is increased. This is described by Ema et al., “3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs”, International Electron Devices Meeting, pp. 592-595, December 1988, and U.S. Pat. Nos. 5,071,783; 5,126,810; and 5,206,787.
Another solution for improving the capacitance of a capacitor is to use the cylindrical-type stacked capacitor. The cylindrical-type stacked capacitor includes electrodes and dielectric films which extend in a cylindrical shape to increase the surface areas of the electrodes. This is described by Wakamiya et al., Novel Stacked Capacitor Cell for 64-Mb DRAM, 1989 Symposium on VLSI Technology Digest of Technical Papers, pp. 69-70, and U.S. Pat. No. 5,077,688.
With the trend toward increased integration density, the size of the DRAM cell must be further reduced. Generally, a reduction in the size of the cell leads to a reduction in charge storage capacitance. Additionally, as the capacitance is reduced, the likelihood of soft errors arising from the incidence of -rays is increased. Therefore, there is still a need in this art to design a new structure and methods for further increasing the capacitance of a storage capacitor while occupying a smaller area in a plane.
SUMMARY OF THE INVENTION
It is an object of the invention to fabricate capacitors using a simple process that is manufacturing cost effective.
It is another object of the invention to provide a capacitor that is more compatible with simplified manufacturing techniques.
According, the present invention provides a method of fabricating a capacitor. The present invention comprises the steps of providing a substrate having a transfer field effect transistor thereon. A first dielectric layer and an etching barrier layer are formed subsequently on the substrate. The first dielectric layer and the etching barrier layer are patterned to form a contact hole therein. The contact hole exposes a source/drain region. A first conductive layer is formed to fill the contact hole and is electrically coupled with the source/drain region. The first conductive layer is patterned to form a raised region on the first conductive layer. The raised region is just above the contact hole. Isolation spacers and conductive spacers are alternately formed on the sidewall of the raised region. Isolation spacers and conductive spacers are interlaced. The isolation spacers are used as mask. An etching barrier layer is used as an etching stop layer. The isolation spacers and a portion of the patterned conductive layer are removed to expose the storage electrode formed by the conductive layer. A second dielectric layer and a second conductive layer are formed on the electrode to be used as cell electrode.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5340763 (1994-08-01), Dennison
patent: 5438013 (1995-08-01), Kim et al.
patent: 5444005 (1995-08-01), Kim et al.
patent: 5482886 (1996-01-01), Park et al.
patent: 5523542 (1996-06-01), Chen et al.
patent: 5837594 (1998-11-01), Honma et al.

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