Television – Image signal processing circuitry specific to television
Reexamination Certificate
1996-12-13
2001-03-20
Faile, Andrew (Department: 2711)
Television
Image signal processing circuitry specific to television
C348S231900
Reexamination Certificate
active
06204889
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an image information processing apparatus for processing image information.
2. Related Background Art
As an image information processing apparatus for processing image information, a data communication system that transmits/receives image data is known.
FIG. 1
is a block diagram showing the arrangement of a conventional data communication system. Referring to
FIG. 1
, a transmission apparatus
100
a
and a receiving apparatus
200
a
constitute the data communication system.
The transmission apparatus
100
a
comprises an A/D converter
1
a
for converting a video signal input from an image input device such as a camera into digital data. The apparatus
100
a
also comprises a memory
2
a
for temporarily storing digital data and a D/A converter
3
a
for converting digital data into analog data.
The apparatus
100
a
further comprises transmission buffers
4
a
,
5
a
, and
6
a
for respectively performing impedance matching of communication lines
9
a
,
10
a
, and
11
a
, a memory controller
7
a
for controlling data read/write accesses to the memory
2
a
, and a clock generator
8
a
for generating clocks to be supplied to the A/D converter
1
a
, the D/A converter
3
a
, and the memory
2
a
. The apparatus
100
a
is connected to the receiving apparatus
200
a
via the communication lines
9
a
,
10
a
, and
11
a.
The receiving apparatus
200
a
comprises reception buffers
12
a
,
13
a
, and
14
a
for respectively performing impedance matching of the communication lines
9
a
,
10
a
, and
11
a
, a clamp circuit
15
a
for converting a signal into a level suitable for an A/D converter
16
a
on its output side, and a memory
17
a
for temporarily storing received data.
The operation of the data communication system will be described below. A video signal input to the A/D converter
1
a
is converted by the A/D converter
1
a
into a digital signal. The converted digital signal is input to and temporarily stored in the memory
2
a
. Note that digital data can be directly input to the memory
2
a
using an external device.
The memory controller
7
a
controls the read/write accesses to the memory
2
a
in accordance with a user's request. The memory
2
a
, the read/write accesses to which are controlled by the memory controller
7
a
, outputs data according to the user's request. Data output from the memory
2
a
is input to the D/A converter
3
a
, and is converted into an analog signal.
The clock generator
8
a
outputs clocks for performing A/D conversion to the A/D converter
1
a
, clocks for controlling the read/write accesses to the memory
2
a
, and clocks for performing D/A conversion to the D/A converter
3
a.
The analog signal D/A-converted by the D/A converter
3
a
is input to the transmission buffer
4
a
. The transmission buffer
4
a
performs impedance matching by amplifying the input analog signal by 6 dB, and sends the analog signal to the reception buffer
12
a
of the receiving apparatus
200
a
via the communication line
9
a.
The clocks supplied to the A/D converter
1
a
, memory
2
a
, and D/A converter
3
a
are similarly input to the transmission buffer
5
a
. The transmission buffer
5
a
performs impedance matching by amplifying the clocks by 6 dB, and sends them to the reception buffer
13
a
via the communication line
10
a.
The analog signal transmitted from the transmission buffer
4
a
is received by the reception buffer
12
a
. The clamp circuit
15
a
converts the received analog signal to a level suitable for A/D conversion. The signal clamped by the clamp circuit
15
a
is input to the A/D converter
16
a
, and is converted into a digital signal. The digital signal is then input to the memory
17
a.
The clocks generated by the clock generator
8
a
are transmitted via the communication line
10
a
and are received by the reception buffer
13
a
. These clocks are supplied as those for the A/D converter
16
a
or those for storing data in the memory
17
a.
On the other hand, data output from the memory
2
a
is sent to the reception buffer
14
a
via the communication line
11
a
. The reception buffer
14
a
outputs the data to the memory
17
a
and stores it therein.
FIG. 2
is a circuit diagram showing the arrangements of the transmission buffer
4
a
and the reception buffer
12
a
. Since the transmission buffer
5
a
and the reception buffer
13
a
respectively have the same arrangements as those of the transmission buffer
4
a
and the reception buffer
12
a
, a detailed description thereof will be omitted. Referring to
FIG. 2
, the transmission buffer
4
a
comprises a transmission operational amplifier
18
a
and a termination resistor
19
a
. Also, the buffer
4
a
comprises a feedback resistor Rf
20
a
and an input resistor Ri
21
a
. The reception buffer
13
a
comprises a termination resistor
22
a
and a reception operational amplifier
23
a
. A signal input to the transmission buffer
4
a
is input to the operational amplifier
18
a
. Note that the feedback resistor (Rf)
20
a
and the input resistor (Ri)
21
a
have the same resistance. At this time, the amplification factor of the operation amplifier
18
a
is 2×, and a gain of 6 dB is obtained. The termination resistors
22
a
and
19
a
respectively have a resistance of 75 &OHgr;. The signal output from the operational amplifier
18
a
is input to the operational amplifier
23
a
via the communication line
9
a
, which is terminated by the termination resistors
19
a
and
22
a
. The signal input to the reception operational amplifier
23
a
is amplified to a gain of 1× by a voltage-follower circuit, and is output to the next stage.
However, the conventional data communication system suffers the following problems. That is, in order to communicate signals such as data, clocks, and the like via the communication lines, the corresponding communication lines, transmission buffers, and reception buffers are required. As a consequence, the size of the data communication system increases, and the number of communication lines increases.
As another conventional image information processing apparatus, an image input apparatus, which fetches an image using a solid-state imaging element such as a CCD and outputs the image to display it on a monitor or to store it in a memory after digital conversion is known.
FIG. 3
is a block diagram showing the arrangement of the conventional image input apparatus. Referring to
FIG. 3
, the apparatus comprises a lens
1201
, an aperture portion
1202
, an optical low-pass filter
1203
with a complementary color mosaic pattern, a CCD
1204
, a gain amplifier
1205
, and an A/D conversion circuit
1206
.
The apparatus also comprises a memory A
1207
, a memory B
1208
, an operation processing circuit
1209
, a selector
1210
, a look-up table (LUT)
1211
, a D/A conversion circuit
1212
, a memory controller
1213
, a CPU
1214
, and a timing generator
1215
.
In the image input apparatus with the above-mentioned arrangement, an image signal input via the lens
1201
passes through the aperture portion
1202
and the optical low-pass filter
1203
, and is supplied to the CCD
1204
. A charge accumulated on the CCD
1204
is read out as an optical image electrical signal by driving the CCD
1204
in accordance with a control signal from the timing generator
1215
, and the readout electrical signal is amplified by the gain amplifier
1205
. Thereafter, the amplified electrical signal is output.
The gain amplifier
1205
is level-controlled by a signal from the timing generator
1215
, which is controlled by the CPU
1214
.
The output signal from the gain amplifier
1205
is converted into a digital signal by the A/D conversion circuit
1206
, and is stored in the memory A
1207
as cyan (Cy), magenta (Mg), yellow (Ye), and green (G) data. On the other hand, the memory B
1208
stores dark signal data. The dark signal data is the one obtained from the CCD
1204
in the light-shielded state by closing the aperture portion
1202
Endoh Shozo
Oiwa Yasuyuki
Brown Reuben
Canon Kabushiki Kaisha
Faile Andrew
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