Electrical audio signal processing systems and devices – Hearing aids – electrical – Programming interface circuitry
Reexamination Certificate
1998-04-16
2001-05-29
Kuntz, Curtis (Department: 2643)
Electrical audio signal processing systems and devices
Hearing aids, electrical
Programming interface circuitry
C381S312000, C381S316000, C381S321000
Reexamination Certificate
active
06240192
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to hearing aids. This invention more particularly relates to an apparatus and method for use in hearing aids that employ digital processing methods to implement hearing loss compensation and other forms of corrective processing.
BACKGROUND OF THE INVENTION
The design of digital hearing aids involves numerous trade-offs between processing capability, flexibility, power consumption and size. Minimizing both chip size and power consumption are important design considerations for integrated circuits used in hearing aids. Fully-programmable implementations of digital hearing aids (i.e., those that use a software-controlled digital signal processor) provide the most flexibility. However, with current technology, a fully-programmable digital signal processor (DSP) chip or core consumes a relatively large amount of power. An application specific processor (typically implemented using an application specific integrated circuit or ASIC) will consume less power and chip-area than a fully-programmable, general-purpose DSP core for equivalent processing capabilities, but is less flexible and adaptable.
Digital hearing aids typically operate at very low supply voltages (1 volt). If circuits for digital hearing aids are fabricated using conventional high-threshold (0.6 volt or greater) semiconductor technology they are not able to operate at high clock speeds (>1 MHz) because of the small difference between the supply voltage and threshold voltage. Even if a DSP core is capable of executing one instruction per clock cycle this limits the computation speed to less than 1 million instructions per second (1 MIPS). This is not a high enough computation rate to implement advanced processing schemes like adaptive noise reduction or multi-band wide dynamic range compression with 16 or more bands. Because ASIC implementations overcome the sequential nature of a typical DSP core and permit calculations to be made in parallel, they can provide more computational capability, i.e. a higher computation rate, and can be used to implement computationally intensive processing strategies.
A major disadvantage of digital hearing aids that are implemented using ASICs is that they are “hardwired” and lack the flexibility required for refinements in processing schemes that will take place over time as knowledge of hearing loss increases. In contrast, digital hearing aids that use programmable DSP cores can be re-programmed to implement a wide range of different processing strategies.
The basic processing strategy used by the vast majority of hearing aids applies frequency specific gain to compensate for hearing loss. Adaptive processing schemes like compression and noise reduction extend this basic processing scheme by adjusting the frequency specific gain in response to changes in input signal conditions.
SUMMARY OF THE INVENTION
The present inventors have realized that an efficient method of implementing this filtering action is the use of a filterbank. A filterbank splits the incoming signal into a number of separate frequency bands. Gains applied to these frequency bands are adjusted independently or in combination as a function of input signal conditions to implement a particular processing strategy. This is disclosed in our copending application Ser. No. 09/060,823, filed simultaneously herewith.
The present invention is based on the realization that significant advantages can be obtained if the benefits of a fully-programmable DSP core are combined with a hardwired ASIC approach. More specifically, the present invention proposes implementing the fixed portion of the processing strategy in an ASIC and using a programmable DSP core or other form of microcontroller to control the parameters of the fixed processing scheme. This combined approach provides improved flexibility and processing capabilities while still achieving low power consumption and small chip size. Thus, the present invention provides a single chip incorporating both a dedicated ASIC and a DSP core, which are partitioned so that they can function independently and in parallel.
More particularly, it is realized that signal processing in a digital filterbank hearing aid, occurs at two different rates. High-speed processing that processes input samples at the sampling rate is used to split the incoming signal into a plurality of frequency bands. The parameters of the processing strategy (e.g., filterbank channel gains) are typically adjusted at a much slower rate (on the order of milliseconds) in response to changes in input signal conditions. The present invention uses an ASIC to implement the high-speed processing and a programmable digital signal processor for the lower-speed processing, to achieve a balance between the conflicting requirements of flexibility, processing capability, size and power consumption.
The present invention therefore provides, in a first aspect, an apparatus, for use in a digital hearing aid, comprising: a dedicated application specific integrated circuit, that includes an oversampled filterbank, which comprises analysis filter means for separating a signal into a plurality of different frequency band signals in different frequency bands and synthesis filter means for recombining the frequency band signals into an output signal, and adapted for efficient processing of the frequency band signals; a programmable digital signal processor for controlling at least some of the parameters of the processing of a dedicated application specific integrated circuit, and for adjusting said parameters at a slower rate than the processing in the dedicated application specific integrated circuit; and a multiplication means connected to the programmable digital signal processor and to the application specific integrated circuit, wherein the multiplication means multiples each band by a desired gain, and wherein the gain for each band is controlled by the programmable digital signal processor; wherein the dedicated application specific integrated circuit and the programmable digital signal processor are integral with one another and are partitioned to enable the dedicated application specific integrated circuit and the digital signal processor to operate independently and in parallel.
REFERENCES:
patent: 4689820 (1987-08-01), Kopke et al.
Brennan Robert
Schneider Anthony Todd
Bereskin & Parr
dspfactory Ltd.
Kuntz Curtis
Ni Suhan
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